u-boot.git/board/xilinx/microblaze-generic, branch master Unnamed repository; edit this file 'description' to name the repository. xilinx: common: fix script address for Microblaze 2024-10-25T12:10:31+00:00 Padmarao Begari padmarao.begari@amd.com 2024-10-01T08:25:37+00:00 5550a152baf612ed8acecc11074f72c40b7c02c1 Fix the issue introduced by commit 067e0294806e ("board: xilinx: Remove conditional check for Microblaze"). The scriptaddr should be physical location not really offset from start of DDR. When U-Boot is not found boot.scr script address in device tree, then it is assigned based on script address and ram base address for Microblaze and i.e exceeding DDR memory. To fix this, the script address is assigned initially with offset instead of address. Later it is added with ram base address and gets the physical address. Signed-off-by: Padmarao Begari <padmarao.begari@amd.com> Link: https://lore.kernel.org/r/20241001082537.830286-1-padmarao.begari@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com> 
Fix the issue introduced by commit 067e0294806e
("board: xilinx: Remove conditional check for Microblaze").
The scriptaddr should be physical location not really offset
from start of DDR. When U-Boot is not found boot.scr script
address in device tree, then it is assigned  based on script
address  and ram base address for Microblaze and i.e exceeding
DDR memory. To fix this, the script address is assigned
initially with offset instead of address. Later it is added
with ram base address and gets the physical address.

Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Link: https://lore.kernel.org/r/20241001082537.830286-1-padmarao.begari@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
board: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD 2024-10-11T17:44:48+00:00 Simon Glass sjg@chromium.org 2024-09-30T01:49:47+00:00 dac3ce976a9b06be5aadbd857c4b64a8c521c6d4 Use the new symbol to refer to any 'SPL' build, including TPL and VPL Signed-off-by: Simon Glass <sjg@chromium.org> 
Use the new symbol to refer to any 'SPL' build, including TPL and VPL

Signed-off-by: Simon Glass <sjg@chromium.org>
Kconfig: Centralize prompting for SYS_CONFIG_NAME 2024-02-27T19:18:54+00:00 Tom Rini trini@konsulko.com 2024-01-22T22:39:20+00:00 3dd1486800d3aa0cff114a34d7dc1cdc3f47c172 Generally speaking, we do not prompt for this value and define it in the board specific Kconfig file. There are some valid use cases however today where we do prompt for this value, so instead of having this be done in a number of locations, do this at the top-level location only. This removes the question from a number of other locations and makes it consistent that when we do set the value directly, we always do it the same way. We don't need to specify the type, it's always string. Signed-off-by: Tom Rini <trini@konsulko.com> 
Generally speaking, we do not prompt for this value and define it in the
board specific Kconfig file. There are some valid use cases however
today where we do prompt for this value, so instead of having this be
done in a number of locations, do this at the top-level location only.

This removes the question from a number of other locations and makes it
consistent that when we do set the value directly, we always do it the
same way. We don't need to specify the type, it's always string.

Signed-off-by: Tom Rini <trini@konsulko.com>
microblaze: Remove common.h usage 2023-10-24T20:34:45+00:00 Tom Rini trini@konsulko.com 2023-10-12T23:03:57+00:00 577dddb5b7d6e0f962ea06ed80b85bc6ec5ca7d8 We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Michal Simek <michal.simek@amd.com> 
We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.

Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Michal Simek <michal.simek@amd.com>
arm64: xilinx: Move board_get_usable_ram_top() to common location 2022-09-13T09:32:48+00:00 Michal Simek michal.simek@amd.com 2022-08-25T12:23:10+00:00 a32c3e9e4fb6932f80a165f56dc52e7afcffb2b2 The commit ce39ee28ec31 ("zynqmp: Do not place u-boot to reserved memory location") adds functionality for ZynqMP to read reserved memory node and do not place U-Boot to reserved location. This functionality is generic across all Xilinx SOCs that's why move it to common location to be used by all Xilinx SOCs. On zynq platform this is also fixing issue where U-Boot was placed to locating which was reserved already which ends up with error message "ERROR: reserving fdt memory region failed (addr=30000000 size=10000000 flags=4)" which is shown when bdinfo is called. Tested on vck190, zcu102, zc706 and kc705 to cover all platforms. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/b0817807912f7c7af6a8e1cf9ee04e5ab5de5f6a.1661430188.git.michal.simek@amd.com 
The commit ce39ee28ec31 ("zynqmp: Do not place u-boot to reserved memory
location") adds functionality for ZynqMP to read reserved memory node and
do not place U-Boot to reserved location. This functionality is generic
across all Xilinx SOCs that's why move it to common location to be used by
all Xilinx SOCs.

On zynq platform this is also fixing issue where U-Boot was placed to
locating which was reserved already which ends up with error message
"ERROR: reserving fdt memory region failed (addr=30000000 size=10000000
flags=4)" which is shown when bdinfo is called.

Tested on vck190, zcu102, zc706 and kc705 to cover all platforms.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b0817807912f7c7af6a8e1cf9ee04e5ab5de5f6a.1661430188.git.michal.simek@amd.com
microblaze: add support for handling PVR data 2022-06-24T12:16:00+00:00 Ovidiu Panait ovpanait@gmail.com 2022-05-31T18:14:34+00:00 9df16c5937f68654fb2b67f932319c375f8e4e45 Add helper code for PVR (Processor Version Register) data handling. It will be used by the UCLASS_CPU driver to populate cpuinfo fields at runtime. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-13-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com> 
Add helper code for PVR (Processor Version Register) data handling. It
will be used by the UCLASS_CPU driver to populate cpuinfo fields at
runtime.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-13-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
microblaze: Kconfig: introduce XILINX_MICROBLAZE0_FPGA_FAMILY option 2022-06-24T12:16:00+00:00 Ovidiu Panait ovpanait@gmail.com 2022-05-31T18:14:33+00:00 064057fdbee085dba17f7afc298deb9ffbf3382a Provide a static Kconfig value for the target FPGA archtitecture, as it is done in Linux. The cpu-uclass driver will cross-check it with the value read from PVR10 register. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-12-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com> 
Provide a static Kconfig value for the target FPGA archtitecture, as it is
done in Linux. The cpu-uclass driver will cross-check it with the value
read from PVR10 register.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-12-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
microblaze: cache: introduce Kconfig options for icache/dcache sizes 2022-06-24T12:16:00+00:00 Ovidiu Panait ovpanait@gmail.com 2022-05-31T18:14:29+00:00 84488fc69348367ee693ea4ab6affe3cbcae97a0 Replace XILINX_DCACHE_BYTE_SIZE macro with two Kconfig symbols for instruction and data caches sizes, respectively: CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE Also, get rid of the hardcoded value in icache_disable(). Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-8-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com> (s/bralid/brlid/g) 
Replace XILINX_DCACHE_BYTE_SIZE macro with two Kconfig symbols for
instruction and data caches sizes, respectively:
CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE
CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE

Also, get rid of the hardcoded value in icache_disable().

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-8-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com> (s/bralid/brlid/g)
microblaze: cache: improve icache Kconfig options 2022-06-24T12:16:00+00:00 Ovidiu Panait ovpanait@gmail.com 2022-05-31T18:14:27+00:00 8daf89678e9a8ce4203d2df6c65d9ff17aad785a Replace CONFIG_ICACHE with a Kconfig option more limited in scope - XILINX_MICROBLAZE0_USE_WIC. It should be enabled if the processor supports the "wic" (Write to Instruction Cache) instruction. It will be used to guard "wic" invocations in microblaze cache code. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-6-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com> 
Replace CONFIG_ICACHE with a Kconfig option more limited in scope -
XILINX_MICROBLAZE0_USE_WIC. It should be enabled if the processor supports
the "wic" (Write to Instruction Cache) instruction. It will be used to
guard "wic" invocations in microblaze cache code.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-6-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
microblaze: cache: improve dcache Kconfig options 2022-06-24T12:16:00+00:00 Ovidiu Panait ovpanait@gmail.com 2022-05-31T18:14:26+00:00 ef0a592ae8e2961519510f48ffe48b655b31610a Replace CONFIG_DCACHE with a Kconfig option more limited in scope - XILINX_MICROBLAZE0_USE_WDC. It should be enabled if the processor supports the "wdc" (Write to Data Cache) instruction. It will be used to guard "wdc" invocations in microblaze cache code. Also, drop all ifdefs around flush_cache() calls and only keep one CONFIG_IS_ENABLED() guard within flush_cache() itself. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-5-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com> 
Replace CONFIG_DCACHE with a Kconfig option more limited in scope -
XILINX_MICROBLAZE0_USE_WDC. It should be enabled if the processor supports
the "wdc" (Write to Data Cache) instruction. It will be used to guard
"wdc" invocations in microblaze cache code.

Also, drop all ifdefs around flush_cache() calls and only keep one
CONFIG_IS_ENABLED() guard within flush_cache() itself.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-5-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>