u-boot.git/board/xilinx/versal/Makefile, branch masterUnnamed repository; edit this file 'description' to name the repository.http://cgit.235523.xyz/u-boot.git/atom/board/xilinx/versal/Makefile?h=master2025-04-16T11:44:44Zxilinx: versal: remove versal loadpdi command2025-04-16T11:44:44ZPrasad Kummariprasad.kummari@amd.com2025-03-27T10:52:00Zurn:sha1:c803720237e77f73e3a63cfffca3fd603150d430
The source code for the versal loadpdi command and the
CONFIG_CMD_VERSAL configuration has been removed. It now utilizes
the fpga load <dev> <address> <length> command to load secure &
non-secure pdi images.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Link: https://lore.kernel.org/r/20250327105200.1262615-4-prasad.kummari@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
arm64: zynqmp: Switch to amd.com emails2023-07-21T07:00:38ZMichal Simekmichal.simek@amd.com2023-07-10T12:35:49Zurn:sha1:174d728471d50415fb60f4bcb560d0552591dfba
Update my and DPs email address to match current setup.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
xilinx: common: Add Makefile to common folder2020-10-27T07:13:32ZMichal Simekmichal.simek@xilinx.com2020-10-20T10:05:14Zurn:sha1:3e315f31cc74e897aebb180aa43d572f5d289949
There is no need to reference files in common folder back. Simply adding
Makefile to this folder does the job because this "common" location is
already wired in main Makefile.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
xilinx: versal: Add new versal loadpdi command2020-08-20T07:49:20ZT Karthik Reddyt.karthik.reddy@xilinx.com2020-06-24T09:23:57Zurn:sha1:526a67eb35cb1b6cea2b269c9690550dee232b74
Versal loadpdi command is used for loading secure & non-secure
pdi images.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arm64: versal: Move common board dtb search2019-10-08T11:14:54ZIbai Erkiagaibai.erkiaga-elorza@xilinx.com2019-10-02T14:57:36Zurn:sha1:fec657bebd77d789a7f9708b79f95225a9c4eeef
Move the exisiting function of getting board dtb from versal to a common
Xilinx folder.
Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arm64: versal: Add support for new Xilinx Versal ACAPs2018-10-16T14:53:21ZMichal Simekmichal.simek@xilinx.com2018-08-22T12:55:27Zurn:sha1:ec48b6c991f400c8583ac2f875d65a8539f0b437
Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine
Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent
Engines with leading-edge memory and interfacing technologies to deliver
powerful heterogeneous acceleration for any application. The Versal AI
Core series has five devices, offering 128 to 400 AI Engines. The series
includes dual-core Arm Cortex™-A72 application processors, dual-core Arm
Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more
than 1,900 DSP engines optimized for high-precision floating point with
low latency.
The patch is adding necessary infrastructure in place without enabling
platform which is done in separate patch.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>