u-boot.git/board/xilinx, branch v2018.07

arm64: zynqmp: Check return value from calloc

2018-06-15T06:54:05Z

calloc() can fail and return NULL. The patch is checking return value and return in case of error. Signed-off-by: Michal Simek

arm: zynq: Add missing watchdog header

2018-06-15T06:06:31Z

Add missing header detected by sparse. Signed-off-by: Michal Simek

arm64: zynqmp: Setup the first boot_target at run time

2018-05-31T11:50:39Z

Detect mmc alias at run time for setting up proper boot_targets sequence. The first target has to correspond with boot mode. The purpose of this patch is to get rid of CONFIG_ZYNQ_SDHCI0/1 parameters in full U-Boot. Unfortunately this patch can't remove it because there is missing mmc implementation for SPL_DM_SEQ_ALIAS. Also xilinx_zynqmp.h only setup boot commands for mmc0 and mmc1. It means using aliases with higher number won't work. But switching between mmc0 and mmc1 should work properly. Signed-off-by: Michal Simek Reviewed-by: Alexander Graf

arm64: zynqmp: Show reset reason

2018-05-31T11:50:39Z

Read reset reason reg and show it in log and also save it as variable. Clearing reset reason when it is read to show only one status Signed-off-by: Michal Simek

arm64: zynqmp: Use DWC3 generic driver and DM_USB

2018-05-18T11:23:15Z

Remove harcoded XHCI lists and detect mode, speed based on DT. Signed-off-by: Michal Simek Serial-changes: 2 - Remove also XHCI macros from hardware.h - Remove additional new line in zcu106

SPDX: Correct SPDX tags from recent xilinx merge

2018-05-11T18:54:57Z

Correct the SPDX tag format. Fixes: 3b52847a451a ("Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze") Signed-off-by: Tom Rini

Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze

2018-05-11T15:45:28Z

Xilinx changes for v2018.07 microblaze: - Align defconfig zynq: - Rework fpga initialization and cpuinfo handling zynqmp: - Add ZynqMP R5 support - Wire and enable watchdog on zcu100-revC - Setup MMU map for DDR at run time - Show board info based on DT and cleanup IDENT_STRING zynqmp tools: - Add read partition support - Add initial support for Xilinx bif format for boot.bin generation mmc: - Fix get_timer usage on 64bit cpus - Add support for SD3.0 UHS mode nand-zynq: - Add support for 16bit buswidth - Use address cycles from onfi params scsi: - convert ceva sata to UCLASS_AHCI timer: - Add Cadence TTC for ZynqMP r5 watchdog: - Minor cadence driver cleanup

mmc: zynq_sdhci: Add support for SD3.0

2018-05-11T09:13:51Z

This patch adds support of SD3.0 for ZynqMP. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek

arm: zynqmp: Add ZynqMP minimal R5 support

2018-05-11T07:38:23Z

Xilinx ZynqMP also contains dual Cortex R5 which can run U-Boot. This patch is adding minimal support to get U-Boot boot. U-Boot on R5 runs out of DDR with default configuration that's why DDR needs to be partitioned if there is something else running on arm64. Console is done via Cadence uart driver and the first Cadence Triple Timer Counter is used for time. This configuration with uart1 was tested on zcu100-revC. U-Boot 2018.05-rc2-00021-gd058a08d907d (Apr 18 2018 - 14:11:27 +0200) Model: Xilinx ZynqMP R5 DRAM: 512 MiB WARNING: Caches not enabled MMC: In: serial@ff010000 Out: serial@ff010000 Err: serial@ff010000 Net: Net Initialization Skipped No ethernet found. ZynqMP r5> There are two ways how to run this on ZynqMP. 1. Run from ZynqMP arm64 tftpb 20000000 u-boot-r5.elf setenv autostart no && bootelf -p 20000000 cpu 4 disable && cpu 4 release 10000000 lockstep or cpu 4 disable && cpu 4 release 10000000 split 2. Load via jtag when directly to R5 Signed-off-by: Michal Simek

arm64: zynqmp: Simplify boot_target variable composition

2018-05-11T07:23:43Z

Call calloc for space allocation only at one location and include if/else to sprintf. This will simplify run time device adding based on id aliases. Signed-off-by: Michal Simek Reviewed-by: Alexander Graf