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<title>u-boot.git/board/xilinx, branch v2018.11</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/board/xilinx?h=v2018.11</id>
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<updated>2018-10-16T14:53:24Z</updated>
<entry>
<title>arm64: zynqmp: Add new command for TCM initialization</title>
<updated>2018-10-16T14:53:24Z</updated>
<author>
<name>Siva Durga Prasad Paladugu</name>
<email>siva.durga.paladugu@xilinx.com</email>
</author>
<published>2018-10-05T09:39:05Z</published>
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<id>urn:sha1:5860bc16b918bb5456a4a77930eafd7c858f70db</id>
<content type='text'>
This patch adds new zynqmp command "zynqmp tcminit mode" to
initialize TCM. TCM needs to be initialized before accessing
to avoid ECC errors. This new command helps to perform
the same. It also makes tcm_init() as global and uses it for
doing the TCM initialization.

Signed-off-by: Siva Durga Prasad Paladugu &lt;siva.durga.paladugu@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
<entry>
<title>arm64: versal: Add support for new Xilinx Versal ACAPs</title>
<updated>2018-10-16T14:53:21Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2018-08-22T12:55:27Z</published>
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<id>urn:sha1:ec48b6c991f400c8583ac2f875d65a8539f0b437</id>
<content type='text'>
Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine
Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent
Engines with leading-edge memory and interfacing technologies to deliver
powerful heterogeneous acceleration for any application. The Versal AI
Core series has five devices, offering 128 to 400 AI Engines. The series
includes dual-core Arm Cortex™-A72 application processors, dual-core Arm
Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more
than 1,900 DSP engines optimized for high-precision floating point with
low latency.

The patch is adding necessary infrastructure in place without enabling
platform which is done in separate patch.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
<entry>
<title>arm: zynq: Add support for DLC20 board</title>
<updated>2018-10-16T12:58:45Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2018-09-13T06:44:02Z</published>
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<id>urn:sha1:6bfe3fffac1bb15b95f9e047224ac57441e46b7e</id>
<content type='text'>
Xilinx DLC20 has I2C0 with EEPROM(1KB), UART1, GPIO, SD0 (EMMC 4GB),
USB0 device, ENET0, QSPI (16MB) and DDR(two of 256MB each).

Boards have mix of Winbond/ST QSPIs.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
<entry>
<title>arm64: zynqmp: Return pmufw version for zynqmp_pmufw_version()</title>
<updated>2018-09-26T08:15:00Z</updated>
<author>
<name>Siva Durga Prasad Paladugu</name>
<email>siva.durga.paladugu@xilinx.com</email>
</author>
<published>2018-08-21T10:14:49Z</published>
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<id>urn:sha1:b94a8271cc42086f3f75941c15bba265f409601d</id>
<content type='text'>
Modify the zynqmp_pmufw_version() routine to return PMUFW version so
that it can be reused wherever required. Get PMUFW version from PMU
only once at bootup and later just return stored value.

Signed-off-by: Siva Durga Prasad Paladugu &lt;siva.durga.paladugu@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
<entry>
<title>zynqmp: Add avnet_ultra96_rev1_defconfig to the lits of boards</title>
<updated>2018-08-07T15:36:39Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-08-07T15:36:39Z</published>
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<id>urn:sha1:b1aad8dbe28415695b290726199681ced969c118</id>
<content type='text'>
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>arm64: zynqmp: Add support for Avnet Ultra96</title>
<updated>2018-08-06T06:44:35Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2018-07-24T14:27:00Z</published>
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<id>urn:sha1:2570e12960486cdf2b1e0e3fb8f6100116ccf65e</id>
<content type='text'>
Avnet Ultra96 is rebranded Xilinx zcu100 revC/D. Add new defconfig files
and point to origin internal board name.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
<entry>
<title>arm: zynq: add support for the zybo z7 board</title>
<updated>2018-08-06T06:44:35Z</updated>
<author>
<name>Luis Araneda</name>
<email>luaraneda@gmail.com</email>
</author>
<published>2018-07-24T15:31:19Z</published>
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<id>urn:sha1:58f449676ac29938ea2970e240a2defe99240a8e</id>
<content type='text'>
The board is manufactured by Digilent
Main features:
- Soc: XC7Z010 (Z7-10) or XC7Z020 (Z7-20)
- RAM: 1 GB DDR3L
- FLASH: 16 MB QSPI
- 1 Gbps Ethernet
- USB 2.0
- microSD slot
- Pcam camera connector
- HDMI Tx and Rx
- Audio codec: stereo out, stereo in, mic
- 5 (Z7-10) or 6 (Z7-20) Pmod ports
- 6 push-buttons, 4 switches, 5 LEDs
- 1 (Z7-10) or 2 (Z7-20) RGB LEDs

Signed-off-by: Luis Araneda &lt;luaraneda@gmail.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
<entry>
<title>microblaze: Add missing quotes around XILINX_MICROBLAZE0_HW_VER</title>
<updated>2018-08-06T06:44:35Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2018-07-23T06:34:43Z</published>
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<id>urn:sha1:8a32077ea61fb0f300cc507876326f336b8b3bef</id>
<content type='text'>
This issue is reported by kconfiglib:
warning: style: quotes recommended around default value for string
symbol XILINX_MICROBLAZE0_HW_VER (defined at
board/xilinx/microblaze-generic/Kconfig:37)

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
<entry>
<title>lib: fdtdec: Rename routine fdtdec_setup_memory_size()</title>
<updated>2018-07-19T08:49:56Z</updated>
<author>
<name>Siva Durga Prasad Paladugu</name>
<email>siva.durga.paladugu@xilinx.com</email>
</author>
<published>2018-07-16T10:26:11Z</published>
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<id>urn:sha1:12308b128fa28d50c1586f60f3117f5213356756</id>
<content type='text'>
This patch renames the routine fdtdec_setup_memory_size()
to fdtdec_setup_mem_size_base() as it now fills the
mem base as well along with size.

Signed-off-by: Siva Durga Prasad Paladugu &lt;siva.durga.paladugu@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;

</content>
</entry>
<entry>
<title>arm64: zynqmp: Added support of mmio read and write commands</title>
<updated>2018-07-19T08:49:56Z</updated>
<author>
<name>Vipul Kumar</name>
<email>vipul.kumar@xilinx.com</email>
</author>
<published>2018-07-16T12:34:22Z</published>
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<id>urn:sha1:0358cee5959fca0fea1074d038359d9d15a5a11e</id>
<content type='text'>
This patch added support of mmio read and write commands. These commands
can be used to read and write registers from the u-boot command line.
It can be useful in debugging.

Signed-off-by: Vipul Kumar &lt;vipul.kumar@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
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