u-boot.git/board/xilinx, branch v2022.07

xilinx: fru: Replace spaces with \0 in detected revision

2022-06-06T07:32:26Z

Also fix board revision field where spaces are used instead of \0. The same change was done for board name by commit 530560b6f8eb ("xilinx: fru: Replace spaces with \0 in detected name"). Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/e069e5134e57899e859786ad8ba48721df6df752.1653911444.git.michal.simek@amd.com

arm64: zynqmp: zynqmp-sm-k26-revA: Fix DP PLL configuration

2022-05-18T11:17:54Z

This patch fixes the DP audio and video PLL configurations for the zynqmp-sm-k26-revA som. The Linux DP driver expects the DP to be using the following PLL config: - DP video PLL should use the VPLL (0x0) - DP audio PLL should use the RPLL (0x3) - DP system time clock PLL should use RPLL (0x3) Register 0xFD1A0070 configures the DP video PLL. Register 0xFD1A0074 configures the DP audio PLL. Register 0xFD1A007C configures the DP system time clock PLL. Signed-off-by: Neal Frager Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/fa7e9abc419c9d7648405d1c62367dbe701d09b8.1652709736.git.michal.simek@amd.com

arm64: zynqmp: zynqmp-zcu102-revA: Fix DP PLL configuration

2022-05-18T11:17:18Z

This patch fixes the DP audio and video PLL configurations for the zynqmp-zcu102-revA evaluation board. The Linux DP driver expects the DP to be using the following PLL config: - DP video PLL should use the VPLL (0x0) - DP audio PLL should use the RPLL (0x3) Register 0xFD1A0070 configures the DP video PLL. Register 0xFD1A0074 configures the DP audio PLL. Signed-off-by: Neal Frager Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/b2eb87758e0cd4844e1754da8c58fce58d9cf683.1651740949.git.michal.simek@amd.com

arm64: zynqmp: zynqmp-zcu106-revA: Fix DP PLL configuration

2022-05-18T11:17:18Z

This patch fixes the DP audio and video PLL configurations for the zynqmp-zcu106-revA evaluation board. The Linux DP driver expects the DP to be using the following PLL config: - DP video PLL should use the VPLL (0x0) - DP audio PLL should use the RPLL (0x3) Register 0xFD1A0070 configures the DP video PLL. Register 0xFD1A0074 configures the DP audio PLL. Signed-off-by: Neal Frager Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/62538b4a04dee28a6fc8ac5b85f8c845a5a76aa4.1651740988.git.michal.simek@amd.com

arm64: zynqmp: zynqmp-zcu106-rev1.0: Fix DP PLL configuration

2022-05-18T11:17:18Z

This patch fixes the DP audio and video PLL configurations for the zynqmp-zcu106-rev1.0 evaluation board. The Linux DP driver expects the DP to be using the following PLL config: - DP video PLL should use the VPLL (0x0) - DP audio PLL should use the RPLL (0x3) Register 0xFD1A0070 configures the DP video PLL. Register 0xFD1A0074 configures the DP audio PLL. Signed-off-by: Neal Frager Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/ae42ad6185418713a473660c8d15903299af7764.1652192319.git.michal.simek@amd.com

xilinx: Handle board_get_usable_ram_top(0) properly

2022-05-13T07:10:02Z

board_get_usable_ram_top() was designed for getting the top most location for U-Boot allocation that's why function itself supports via total_size parameter to find out where the right location for U-Boot is. But function itself is also reused by different (EFI) which is passing total_size as 0 to find out where the usable ram top is. For this case doesn't make sense (a waste time) to call any lmb functions. That's why simply return gd->ram_top. And gd->ram_top is filled already based on previous call for U-Boot iself. The same solution is also used by stm32mp by commit 92b611e8b003 ("stm32mp: correctly handle board_get_usable_ram_top(0)") and commit c8510e397fad ("stm32mp: Fix board_get_usable_ram_top()"). Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/44470619e74f3e480b70deac24578e3e0d5c907e.1651225945.git.michal.simek@amd.com

xilinx: versal: board: use CONFIG_COUNTER_FREQUENCY

2022-04-21T18:32:40Z

Since versal has CONFIG_COUNTER_FREQUENCY, so use it. And COUNTER_FREQUENCY will be dropped. Signed-off-by: Peng Fan Reviewed-by: Michal Simek

.mailmap: Start to use new amd.com email address

2022-04-19T18:51:11Z

Xilinx has been acquired by AMD that's why emails should be also updated. The patch is updating .mailmap file and also MAINTAINERS files as was done by commit 5cd1ecb99490 ("ppc: qemu: Update MAINTAINERS for correct email address"). The rest of my emails are not going to change. Signed-off-by: Michal Simek Signed-off-by: Michal Simek

capsule: board: Add information needed for capsule updates

2022-04-15T08:43:18Z

Add a structure which defines the information that is needed for executing capsule updates on a platform. Some information in the structure like the dfu string is used for making the update process more robust while some information like the per platform image GUIDs is used for fixing issues. Initialise this structure in the board file, and use the information for the capsule updates. Signed-off-by: Sughosh Ganu

arm64: zynqmp: Record ID code for XCZU1EG device

2022-04-05T13:11:35Z

Add ID code for 1eg device. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/5b6c9f6a25bba076f304bc4699f6f676a929a683.1648619516.git.michal.simek@xilinx.com