Today we typically enable CMD_SATA in order to have the SATA functionality itself enabled, despite there being a clean split between the two symbols. This in turn leads to potential configuration problems. Split things so that SATA continues to be separate and not CMD_SATA instead depends, functionally, on AHCI being enabled. To do all of this: - Have X86 select AHCI directly rather than "default y" it later. - Make CMD_SATA be a default y option, given the split of platforms that enabled SATA and did, or did not, enable CMD_SATA. - Change "imply CMD_SATA" to "imply SATA" - Correct TARGET_VEXPRESS64_JUNO because you cannot select SATA_SIL without PCI (and in turn, SATA is needed for SATA_SIL). - Update a number of defconfigs to have no functional change. Signed-off-by: Tom Rini <trini@konsulko.com>
It is not functionally possible to use the code enabled by PARTITION_TYPE_GUID without having EFI_PARTITION be enabled as well. Not all users of the former had ensured that the latter was enabled however, so audit all current users and then as appropriate select or imply EFI_PARTITION as needed. Signed-off-by: Tom Rini <trini@konsulko.com>
All information is contained in the global MAINTAINERS or TQ board MAINTAINERS. Signed-off-by: Max Merchel <Max.Merchel@ew.tq-group.com>
Add MAINTAINERS file containing board-specific information and the name of the board maintainer. Signed-off-by: Max Merchel <Max.Merchel@ew.tq-group.com>
Introduce timing patch which converts 2 GiB DRAM timings to 4 GiB 1-rank timings. This is a new configuration which carries IS43LQ32K01B DRAM part. The 512 MiB SoM strapping that was never used is repurposed for this part. Signed-off-by: Marek Vasut <marex@nabladev.com>
The 2 GiB and 4 GiB 2-rank DRAM timings on i.MX8MP DHCOM are very similar. Instead of carrying around two copies of almost identical timing tables, implement a patch of the 2 GiB table to convert it into 4 GiB 2-rank table and pass the result to DRAM initialization code. This saves us 13640 Bytes in SPL, and frees up space for more DRAM initialization tables. Signed-off-by: Marek Vasut <marex@nabladev.com>
The DRAM size tables are shared by SPL and U-Boot proper, deduplicate those tables into lpddr4_timing.h . No functional change. Signed-off-by: Marek Vasut <marex@nabladev.com>
The inline ECC configuration is identical for 2 GiB DRAM variants and 4 GiB DRAM variants of the SoM, no matter the rank count. Fold the ECC configuration directly into spl.c to simplify the upcoming deduplication. No functional change. Signed-off-by: Marek Vasut <marex@nabladev.com>
Convert the board to use DM_PMIC instead of the legacy SPL I2C/PMIC handling. Changes include: - Enable DM_PMIC, DM_PMIC_PCA9450, and SPL_DM_PMIC_PCA9450 in defconfig. - Drop legacy SPL I2C and PMIC options. - Remove manual I2C1 pad setup and legacy power_pca9450_init() usage. - Use DM-based pmic_get() with the DT node "pmic@25". - Update PMIC register programming to use struct udevice API. Signed-off-by: Peng Fan <peng.fan@nxp.com>
Convert the board to use DM_PMIC instead of the legacy SPL I2C/PMIC handling. Changes include: - Enable DM_PMIC, DM_PMIC_PCA9450, and SPL_DM_PMIC_PCA9450 in defconfig. - Drop legacy SPL I2C and PMIC options. - Remove manual I2C1 pad setup and legacy power_pca9450_init() usage. - Use DM-based pmic_get() with the DT node "pmic@25". - Update PMIC register programming to use struct udevice API. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Yannic Moog <y.moog@phytec.de> Tested-by: Yannic Moog <y.moog@phytec.de> Reviewed-by: Teresa Remmet <t.remmet@phytec.de>