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<title>u-boot.git/board, branch v2009.01-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx</title>
<updated>2009-01-13T23:26:48+00:00</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2009-01-13T23:26:48+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=bae6d5e4122882fdeeefdd0358ec592c01abe138'/>
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<pre>
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<entry>
<title>Some changes of TLB entry setting for MPC8572DS</title>
<updated>2009-01-13T22:58:46+00:00</updated>
<author>
<name>Haiying Wang</name>
<email>Haiying.Wang@freescale.com</email>
</author>
<published>2009-01-13T21:29:28+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b5f65dfa9aa8e068e62aba4733dc4fd97b1d9bf6'/>
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- Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode,
all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0
can not access PIXIS_BASE anymore (any access will cause DataTLBError exception)

- Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board.

Signed-off-by: Haiying Wang &lt;Haiying.Wang@freescale.com&gt;
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- Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode,
all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0
can not access PIXIS_BASE anymore (any access will cause DataTLBError exception)

- Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board.

Signed-off-by: Haiying Wang &lt;Haiying.Wang@freescale.com&gt;
</pre>
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</entry>
<entry>
<title>Change PCIE1&amp;2 deciide logic on MPC8544DS board more readable</title>
<updated>2009-01-13T22:32:53+00:00</updated>
<author>
<name>Roy Zang</name>
<email>tie-fei.zang@freescale.com</email>
</author>
<published>2009-01-09T08:02:35+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6d3a10f73ece7ffb736890c10e023222612a4aa0'/>
<id>6d3a10f73ece7ffb736890c10e023222612a4aa0</id>
<content type='text'>
The IO port selection for MPC8544DS board:
 Port			cfg_io_ports
 PCIE1		0x2, 0x3, 0x4, 0x5, 0x6, 0x7
 PCIE2		0x4, 0x5, 0x6, 0x7
 PCIE3		0x6, 0x7
 This patch changes the PCIE12 and PCIE2 logic more readable.
Signed-off-by: Roy Zang &lt;tie-fei.zang@freescale.com&gt;
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The IO port selection for MPC8544DS board:
 Port			cfg_io_ports
 PCIE1		0x2, 0x3, 0x4, 0x5, 0x6, 0x7
 PCIE2		0x4, 0x5, 0x6, 0x7
 PCIE3		0x6, 0x7
 This patch changes the PCIE12 and PCIE2 logic more readable.
Signed-off-by: Roy Zang &lt;tie-fei.zang@freescale.com&gt;
</pre>
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</entry>
<entry>
<title>PCIE2 and PCIE3 are decided by corresponing bit in devdisr instead of PCIE1 bit</title>
<updated>2009-01-13T22:32:52+00:00</updated>
<author>
<name>Roy Zang</name>
<email>tie-fei.zang@freescale.com</email>
</author>
<published>2009-01-09T08:01:52+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=028e116811d28a031660f1ad9e20ac1293b3c5c7'/>
<id>028e116811d28a031660f1ad9e20ac1293b3c5c7</id>
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PCIE2 and PCIE3 should be decided by corresponing bit in devdisr instead of
PCIE1 bit.
On MPC8572DS board, PCIE refers to PCIE1.
Signed-off-by: Roy Zang &lt;tie-fei.zang@freescale.com&gt;
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<pre>
PCIE2 and PCIE3 should be decided by corresponing bit in devdisr instead of
PCIE1 bit.
On MPC8572DS board, PCIE refers to PCIE1.
Signed-off-by: Roy Zang &lt;tie-fei.zang@freescale.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>Fix IO port selection issue on MPC8544DS and MPC8572DS boards</title>
<updated>2009-01-13T22:32:52+00:00</updated>
<author>
<name>Roy Zang</name>
<email>tie-fei.zang@freescale.com</email>
</author>
<published>2009-01-09T08:00:55+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9afc2ef0307aecf52482df67c31b75d5f9e66b47'/>
<id>9afc2ef0307aecf52482df67c31b75d5f9e66b47</id>
<content type='text'>
The IO port selection is not correct on MPC8572DS and MPC8544DS board.
 This patch fixes this issue.
 For MPC8572
 Port			cfg_io_ports
 PCIE1		0x2, 0x3, 0x7, 0xb, 0xc, 0xf
 PCIE2		0x3, 0x7
 PCIE3		0x7

For MPC8544
Port			cfg_io_ports
PCIE1		0x2, 0x3, 0x4, 0x5, 0x6, 0x7
PCIE2		0x4, 0x5, 0x6, 0x7
PCIE3		0x6, 0x7
Signed-off-by: Roy Zang &lt;tie-fei.zang@freescale.com&gt;
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<pre>
The IO port selection is not correct on MPC8572DS and MPC8544DS board.
 This patch fixes this issue.
 For MPC8572
 Port			cfg_io_ports
 PCIE1		0x2, 0x3, 0x7, 0xb, 0xc, 0xf
 PCIE2		0x3, 0x7
 PCIE3		0x7

For MPC8544
Port			cfg_io_ports
PCIE1		0x2, 0x3, 0x4, 0x5, 0x6, 0x7
PCIE2		0x4, 0x5, 0x6, 0x7
PCIE3		0x6, 0x7
Signed-off-by: Roy Zang &lt;tie-fei.zang@freescale.com&gt;
</pre>
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</entry>
<entry>
<title>mpc8610hpcd: Fix PCI mapping concepts</title>
<updated>2009-01-13T21:27:46+00:00</updated>
<author>
<name>Becky Bruce</name>
<email>beckyb@kernel.crashing.org</email>
</author>
<published>2008-12-04T04:36:44+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3e3fffe3baf3befde287fec1fcbfe55052fb8946'/>
<id>3e3fffe3baf3befde287fec1fcbfe55052fb8946</id>
<content type='text'>
Rename _BASE to _BUS, as it's actually a PCI bus address,
separate virtual and physical addresses into _VIRT and _PHYS,
and use each appopriately.  This makes the code easier to read
and understand, and facilitates mapping changes going forward.

Signed-off-by: Becky Bruce &lt;beckyb@kernel.crashing.org&gt;
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<pre>
Rename _BASE to _BUS, as it's actually a PCI bus address,
separate virtual and physical addresses into _VIRT and _PHYS,
and use each appopriately.  This makes the code easier to read
and understand, and facilitates mapping changes going forward.

Signed-off-by: Becky Bruce &lt;beckyb@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sbc8641d: Fix PCI mapping concepts</title>
<updated>2009-01-13T21:27:45+00:00</updated>
<author>
<name>Becky Bruce</name>
<email>beckyb@kernel.crashing.org</email>
</author>
<published>2008-12-04T04:36:26+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=79e436cad3b4a7db88408c3f05175028f30d700d'/>
<id>79e436cad3b4a7db88408c3f05175028f30d700d</id>
<content type='text'>
Rename _BASE to _BUS, as it's actually a PCI bus address,
separate virtual and physical addresses into _VIRT and _PHYS,
and use each appopriately.  This makes the code easier to read
and understand, and facilitates mapping changes going forward.

Signed-off-by: Becky Bruce &lt;beckyb@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Rename _BASE to _BUS, as it's actually a PCI bus address,
separate virtual and physical addresses into _VIRT and _PHYS,
and use each appopriately.  This makes the code easier to read
and understand, and facilitates mapping changes going forward.

Signed-off-by: Becky Bruce &lt;beckyb@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-blackfin</title>
<updated>2009-01-10T17:18:37+00:00</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2009-01-10T17:18:37+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=950309c6436ff78d2166377da34bfdb0ae00a4a4'/>
<id>950309c6436ff78d2166377da34bfdb0ae00a4a4</id>
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<pre>
</pre>
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</entry>
<entry>
<title>bf537-stamp/nand: fix board_nand_init prototype</title>
<updated>2009-01-07T08:00:22+00:00</updated>
<author>
<name>Mike Frysinger</name>
<email>vapier@gentoo.org</email>
</author>
<published>2009-01-05T21:09:44+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=032a1c934ef4dc003281f57302b6e693062c1868'/>
<id>032a1c934ef4dc003281f57302b6e693062c1868</id>
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The board_nand_init() function should return an int, not void.

Signed-off-by: Mike Frysinger &lt;vapier@gentoo.org&gt;
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The board_nand_init() function should return an int, not void.

Signed-off-by: Mike Frysinger &lt;vapier@gentoo.org&gt;
</pre>
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</content>
</entry>
<entry>
<title>Blackfin: fix out-of-tree building with ldscripts</title>
<updated>2009-01-07T07:59:50+00:00</updated>
<author>
<name>Mike Frysinger</name>
<email>vapier@gentoo.org</email>
</author>
<published>2008-10-24T21:51:57+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e7e684b10d73a303902208594c7c3e7e0d753282'/>
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<content type='text'>
Many of the Blackfin board linker scripts are preprocessed, so make sure we
output the linker script into the build tree rather than the source tree.

Signed-off-by: Mike Frysinger &lt;vapier@gentoo.org&gt;
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Many of the Blackfin board linker scripts are preprocessed, so make sure we
output the linker script into the build tree rather than the source tree.

Signed-off-by: Mike Frysinger &lt;vapier@gentoo.org&gt;
</pre>
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