Between v2015.07-rc1 and v2015.07-rc2 this board started
silent boot failure.  A bisect led to commit 6eed3786c68c8a49d
("net: Move the CMD_NET config to defconfigs").  This commit
looks harmless in itself, but it did implicitly add a feature
to the image which led to this:

 u-boot$git describe 6eed3786c68c8a49d
 v2015.07-rc1-412-g6eed3786c68c
              ^^^

 u-boot$ls -l ../41*/u-boot.bin
 -rwxrwxr-x 1 paul paul 261476 Oct 16 16:47 ../411/u-boot.bin
 -rwxrwxr-x 1 paul paul 266392 Oct 16 16:43 ../412/u-boot.bin
 u-boot$bc
 bc 1.06.95
 Copyright 1991-1994, 1997, 1998, 2000, 2004, 2006 Free Software Foundation, Inc.
 This is free software with ABSOLUTELY NO WARRANTY.
 For details type `warranty'.
 256*1024
 262144

i.e. we finally broke through the 256k monitor size.  Jump it
up to 384k and fix the hard coded value used in the env offset
at the same time.

We were probably flirting with the 256k size issue without
knowing it when testing on different baselines in earlier
commits, but since this is all board specific, a rebase or
reorder to put this commit 1st is of little value.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>

...so that I don't have to go work them out from scratch again
by peering at the manual.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>

Juno R1 has an XpressRICH3 PCIe host bridge that needs to be initialised
in order for the Linux kernel to be able to enumerate the bus. Add
support code here that enables the host bridge, trains the links and
sets up the Address Translation Tables.

Signed-off-by: Liviu Dudau <Liviu.Dudau@foss.arm.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
[trini: Always declare vexpress64_pcie_init and continue handling logic
inside the function]
Signed-off-by: Tom Rini <trini@konsulko.com>

Juno comes with 8GB RAM, but U-Boot only passes 2GB to the kernel.
Declare a secondary memory bank and set the sizes correctly.

Signed-off-by: Liviu Dudau <Liviu.Dudau@foss.arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>

Upon further review when populating README.scrapyard, d2net_v2 is a
variant on net2big_v2 and not just an orphan config.  To help in the
future also add this to board/LaCie/net2big_v2/MAINTAINERS which needed
a little consolidation anyhow.

This reverts commit 1363740e7948a8e4bee8d5adcdf0f63f7782879d.

Cc: Simon Guinot <simon.guinot@sequanux.org>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>

Seen this one in the wild. Is labelled "Raspberry Pi Model A+ V1.1,
(C) Raspberry Pi 2014". A standard A+ board, much like the one with
version 0x12, didn't notice any differencies.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>

On keystone2 Lamarr and Edison platforms, the PA clocksource
mux in PLL REG1, can be changed only after enabling its clock
domain.
So selecting the output of PASS PLL as input to PA only after
enabling the clockdomain.
This is as per the debug done by "Vitaly Andrianov <vitalya@ti.com>"
and based on the previous work done by "Hao Zhang <hzhang@ti.com>"

Fixes: d634a0775bcf ("ARM: keystone2: Cleanup PLL init code")
Reported-by: Vitaly Andrianov <vitalya@ti.com>
Tested-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

This commit fixes a typo in vf610twr DRAM init that was causing a hang in
U-Boot for the Vybrid Tower. This typo was introduced in commit 3f353cecc
(vf610: refactor DDRMC code).

Signed-off-by: Anthony Felice <tony.felice@timesys.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>