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<title>u-boot.git/board, branch v2016.05</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>arm: socfpga: Update iomux and pll for c5 socdk RevE</title>
<updated>2016-05-10T21:32:42+00:00</updated>
<author>
<name>Dinh Nguyen</name>
<email>dinguyen@kernel.org</email>
</author>
<published>2016-05-10T20:13:59+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4baca92001bff3c32a05001a7dc58996623e3ef8'/>
<id>4baca92001bff3c32a05001a7dc58996623e3ef8</id>
<content type='text'>
Update the pinmux and pll configuration for the Cyclone5 RevE or later devkit.

Signed-off-by: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
</content>
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<pre>
Update the pinmux and pll configuration for the Cyclone5 RevE or later devkit.

Signed-off-by: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Fix various typos, scattered over the code.</title>
<updated>2016-05-06T01:39:26+00:00</updated>
<author>
<name>Robert P. J. Day</name>
<email>rpjday@crashcourse.ca</email>
</author>
<published>2016-05-04T08:47:31+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1cc0a9f49657734c54939f03fc1e3ca0ec9d7eef'/>
<id>1cc0a9f49657734c54939f03fc1e3ca0ec9d7eef</id>
<content type='text'>
Spelling corrections for (among other things):

* environment
* override
* variable
* ftd (should be "fdt", for flattened device tree)
* embedded
* FTDI
* emulation
* controller
</content>
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<pre>
Spelling corrections for (among other things):

* environment
* override
* variable
* ftd (should be "fdt", for flattened device tree)
* embedded
* FTDI
* emulation
* controller
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: tegra: import latest Jetson TK1 spreadsheet</title>
<updated>2016-05-04T20:31:04+00:00</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2016-04-21T22:03:37+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=bbca7108db79076d3a9a9c112792d7c4608a665c'/>
<id>bbca7108db79076d3a9a9c112792d7c4608a665c</id>
<content type='text'>
This imports v11 of "Jetson TK1 Development Platform Pin Mux" from
https://developer.nvidia.com/embedded/downloads.

The new version defines the mux option for the MIPI pad ctrl selection.
The OWR pin no longer has an entry in the configuration table because
the only mux option it support is OWR, that feature isn't supported, and
hence can't conflict with any other pin. This pin can only usefully be
used as a GPIO.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
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<pre>
This imports v11 of "Jetson TK1 Development Platform Pin Mux" from
https://developer.nvidia.com/embedded/downloads.

The new version defines the mux option for the MIPI pad ctrl selection.
The OWR pin no longer has an entry in the configuration table because
the only mux option it support is OWR, that feature isn't supported, and
hence can't conflict with any other pin. This pin can only usefully be
used as a GPIO.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Fix spelling of "occurred".</title>
<updated>2016-05-02T22:37:09+00:00</updated>
<author>
<name>Vagrant Cascadian</name>
<email>vagrant@debian.org</email>
</author>
<published>2016-05-01T02:18:00+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=eae4b2b67bc8c68e2440616a447ca6c6898ad188'/>
<id>eae4b2b67bc8c68e2440616a447ca6c6898ad188</id>
<content type='text'>
Signed-off-by: Vagrant Cascadian &lt;vagrant@debian.org&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
Signed-off-by: Vagrant Cascadian &lt;vagrant@debian.org&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Change my mailaddress</title>
<updated>2016-05-02T22:37:09+00:00</updated>
<author>
<name>Andreas Bießmann</name>
<email>andreas.devel@googlemail.com</email>
</author>
<published>2016-05-01T01:46:16+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=09c2b8f3e39925e5bdff12cb90add09bc9e117d4'/>
<id>09c2b8f3e39925e5bdff12cb90add09bc9e117d4</id>
<content type='text'>
I'll switch my mails to my own server, so drop all gmail references.

Signed-off-by: Andreas Bießmann &lt;andreas.devel@googlemail.com&gt;
</content>
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<pre>
I'll switch my mails to my own server, so drop all gmail references.

Signed-off-by: Andreas Bießmann &lt;andreas.devel@googlemail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: DRA7: Add ABB setup for all domains</title>
<updated>2016-04-25T19:10:41+00:00</updated>
<author>
<name>Nishanth Menon</name>
<email>nm@ti.com</email>
</author>
<published>2016-04-21T19:34:25+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e52e334e5cb493e19377d23a00aa4d021fc229ba'/>
<id>e52e334e5cb493e19377d23a00aa4d021fc229ba</id>
<content type='text'>
ABB should be initialized for all required domains voltage domain
for DRA7: IVA, GPU, EVE in addition to the existing MPU domain. If
we do not do this, kernel configuring just the frequency using the
default boot loader configured voltage can fail on many corner lot
units and has been hard to debug. This specifically is a concern with
DRA7 generation of SoCs since other than VDD_MPU, all other domains
are only permitted to setup the voltages to required OPP only at boot.

Reported-by: Richard Woodruff &lt;r-woodruff2@ti.com&gt;
Signed-off-by: Nishanth Menon &lt;nm@ti.com&gt;
</content>
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<pre>
ABB should be initialized for all required domains voltage domain
for DRA7: IVA, GPU, EVE in addition to the existing MPU domain. If
we do not do this, kernel configuring just the frequency using the
default boot loader configured voltage can fail on many corner lot
units and has been hard to debug. This specifically is a concern with
DRA7 generation of SoCs since other than VDD_MPU, all other domains
are only permitted to setup the voltages to required OPP only at boot.

Reported-by: Richard Woodruff &lt;r-woodruff2@ti.com&gt;
Signed-off-by: Nishanth Menon &lt;nm@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: OMAP5/DRA7: Move ABB TXDONE mask to voltage structure</title>
<updated>2016-04-25T19:10:39+00:00</updated>
<author>
<name>Nishanth Menon</name>
<email>nm@ti.com</email>
</author>
<published>2016-04-21T19:34:23+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3708e78c33b3853e300a6ded3113de90dacbc633'/>
<id>3708e78c33b3853e300a6ded3113de90dacbc633</id>
<content type='text'>
ABB TX_DONE mask will vary depending on ABB module. For example,
3630 never had ABB on IVA domain, while OMAP5 does use ABB on MM domain,
DRA7 has it on all domains with the exception of CORE, RTC.

Hence, move the txdone mask definition over to structure describing
voltage domain.

Signed-off-by: Nishanth Menon &lt;nm@ti.com&gt;
</content>
<content type='xhtml'>
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<pre>
ABB TX_DONE mask will vary depending on ABB module. For example,
3630 never had ABB on IVA domain, while OMAP5 does use ABB on MM domain,
DRA7 has it on all domains with the exception of CORE, RTC.

Hence, move the txdone mask definition over to structure describing
voltage domain.

Signed-off-by: Nishanth Menon &lt;nm@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: hikey: Simplify README instructions.</title>
<updated>2016-04-25T19:10:36+00:00</updated>
<author>
<name>Peter Griffin</name>
<email>peter.griffin@linaro.org</email>
</author>
<published>2016-04-20T16:14:03+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=532d5203e972092cb1029e49d906f28a0895ca39'/>
<id>532d5203e972092cb1029e49d906f28a0895ca39</id>
<content type='text'>
This patch updates and simplifies the hikey README. The old
instructions were hard to follow, and convoluted.

This patch also updates the link to the mcuimage.bin which was outdated.

Using an outdated mcuimage.bin results in the additional a53 cores
not coming online when the kernel issues PSCI requests to
arm trusted firmware (ATF).

Signed-off-by: Peter Griffin &lt;peter.griffin@linaro.org&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
<content type='xhtml'>
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<pre>
This patch updates and simplifies the hikey README. The old
instructions were hard to follow, and convoluted.

This patch also updates the link to the mcuimage.bin which was outdated.

Using an outdated mcuimage.bin results in the additional a53 cores
not coming online when the kernel issues PSCI requests to
arm trusted firmware (ATF).

Signed-off-by: Peter Griffin &lt;peter.griffin@linaro.org&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: hisilicon: hikey: Align memory node with upstream kernel</title>
<updated>2016-04-25T19:10:35+00:00</updated>
<author>
<name>Peter Griffin</name>
<email>peter.griffin@linaro.org</email>
</author>
<published>2016-04-20T16:14:02+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=305b90919ea8c17edeb1e7d15ae5ca43f36bddc2'/>
<id>305b90919ea8c17edeb1e7d15ae5ca43f36bddc2</id>
<content type='text'>
The memory node gets automatically generated by U-Boot
in arch_fixup_fdt(), before passing control to the kernel
using U-Boots representation of the dram banks.

However the upstream kernel uses the memory node to carve-out
regions of RAM for various purposes. To make this work without
changing arch_fixup_fdt() which will effect many platforms
we replicate the upstream memory node layout using the dram
banks.

Signed-off-by: Peter Griffin &lt;peter.griffin@linaro.org&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The memory node gets automatically generated by U-Boot
in arch_fixup_fdt(), before passing control to the kernel
using U-Boots representation of the dram banks.

However the upstream kernel uses the memory node to carve-out
regions of RAM for various purposes. To make this work without
changing arch_fixup_fdt() which will effect many platforms
we replicate the upstream memory node layout using the dram
banks.

Signed-off-by: Peter Griffin &lt;peter.griffin@linaro.org&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: hisilicon: hikey: Implement reset_cpu() for hikey.</title>
<updated>2016-04-25T19:10:34+00:00</updated>
<author>
<name>Peter Griffin</name>
<email>peter.griffin@linaro.org</email>
</author>
<published>2016-04-20T16:14:00+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9261f8b1809d6bf2075cfc97bbd0cac23e086716'/>
<id>9261f8b1809d6bf2075cfc97bbd0cac23e086716</id>
<content type='text'>
This allows the reset command to reset the board from
u-boot.

=&gt; reset
resetting ...
INFO:    BL1: 0xf9810000 - 0xf9818000 [size = 32768]
NOTICE:  Booting Trusted Firmware
NOTICE:  BL1: v1.1(debug):7fb9b0e
NOTICE:  BL1: Built : 17:06:41, Apr 19 2016

Signed-off-by: Peter Griffin &lt;peter.griffin@linaro.org&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This allows the reset command to reset the board from
u-boot.

=&gt; reset
resetting ...
INFO:    BL1: 0xf9810000 - 0xf9818000 [size = 32768]
NOTICE:  Booting Trusted Firmware
NOTICE:  BL1: v1.1(debug):7fb9b0e
NOTICE:  BL1: Built : 17:06:41, Apr 19 2016

Signed-off-by: Peter Griffin &lt;peter.griffin@linaro.org&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
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