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<title>u-boot.git/board, branch v2019.10</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/board?h=v2019.10</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/board?h=v2019.10'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2019-10-06T19:20:53Z</updated>
<entry>
<title>MAINTAINERS: Update my email address</title>
<updated>2019-10-06T19:20:53Z</updated>
<author>
<name>Maxime Ripard</name>
<email>mripard@kernel.org</email>
</author>
<published>2019-10-03T16:32:11Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9bd9b2bcbee1c0a0c2fcc2d5e2c61ea272e865c5'/>
<id>urn:sha1:9bd9b2bcbee1c0a0c2fcc2d5e2c61ea272e865c5</id>
<content type='text'>
I'm not at bootlin anymore, and my mail address doesn't work any longer.

Signed-off-by: Maxime Ripard &lt;mripard@kernel.org&gt;
</content>
</entry>
<entry>
<title>ARM: dts: imx6q-logicpd: Add missing imx6q-logicpd-u-boot for SPL</title>
<updated>2019-10-04T16:21:23Z</updated>
<author>
<name>Adam Ford</name>
<email>aford173@gmail.com</email>
</author>
<published>2019-08-07T15:16:33Z</published>
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<id>urn:sha1:5ff1963da31767521cbb755c0aa1f8ed2e361efd</id>
<content type='text'>
The SPL device tree is missing the entires for gpio1, uart1, usdhc1 and
usdhc2.  This creates the missing imx6q-logicpd-u-boot.dtsi file
which will enable these functions so SPL can properly setup UART, detect
microSD card, and startup.

Fixes: 8f4691e31a18 ("ARM: imx6q_logic: With SPL_OF_CONTROL enabled,
remove MMC init")

Signed-off-by: Adam Ford &lt;aford173@gmail.com&gt;
</content>
</entry>
<entry>
<title>board: ti: am654: Disable TRNG node for HS devices</title>
<updated>2019-10-04T16:21:23Z</updated>
<author>
<name>Andrew F. Davis</name>
<email>afd@ti.com</email>
</author>
<published>2019-09-17T21:15:40Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=29c9db4d98711606c48d130f328f848fa7adae55'/>
<id>urn:sha1:29c9db4d98711606c48d130f328f848fa7adae55</id>
<content type='text'>
On HS devices the access to TRNG is restricted on the non-secure
ARM side, disable the node in DT to prevent firewall violations.

Signed-off-by: Andrew F. Davis &lt;afd@ti.com&gt;
Reviewed-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
</content>
</entry>
<entry>
<title>rpi4: enable dram bank initialization</title>
<updated>2019-10-01T09:14:47Z</updated>
<author>
<name>Matthias Brugger</name>
<email>mbrugger@suse.com</email>
</author>
<published>2019-09-09T16:31:56Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9de5b89e4c898ec770878eb4848588c635a37bac'/>
<id>urn:sha1:9de5b89e4c898ec770878eb4848588c635a37bac</id>
<content type='text'>
When booting through the efi stub, the memory map get's created by
reading the dram bank information. Depending on the version of the RPi4
this information changes. Read the device tree to initialize the dram
bank data structure. This way the kernel is able to access the whole
range of available memory.

Signed-off-by: Matthias Brugger &lt;mbrugger@suse.com&gt;
</content>
</entry>
<entry>
<title>Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq</title>
<updated>2019-09-16T17:13:45Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2019-09-16T17:13:45Z</published>
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<id>urn:sha1:a9fa70b7b7167487affc5d919e541872c99e814b</id>
<content type='text'>
- Add emmc hs200 support
- Few bug fixes related to serdes, I2C, ethernet, etc
</content>
</entry>
<entry>
<title>MAINTAINERS: Change fsl-qoriq, mpc86xx, mpc85xx maintainers</title>
<updated>2019-09-13T14:14:45Z</updated>
<author>
<name>Priyanka Jain</name>
<email>priyanka.jain@nxp.com</email>
</author>
<published>2019-09-09T11:25:08Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=87d5b225585f341ea8e926a2c26fb72585fc9d0c'/>
<id>urn:sha1:87d5b225585f341ea8e926a2c26fb72585fc9d0c</id>
<content type='text'>
Change maintainers to Priyanka Jain for fsl-qoriq, mpc85xx

Signed-off-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
Acked-by: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
</content>
</entry>
<entry>
<title>lx2160: Correct serdes frequency print.</title>
<updated>2019-09-12T10:45:42Z</updated>
<author>
<name>Meenakshi Aggarwal</name>
<email>meenakshi.aggarwal@nxp.com</email>
</author>
<published>2019-09-04T11:09:56Z</published>
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<id>urn:sha1:737c016d25d6c45e9c003fca9df2ca75f0b1e772</id>
<content type='text'>
Suffix serdes frequency print with MHz

Signed-off-by: Meenakshi Aggarwal &lt;meenakshi.aggarwal@nxp.com&gt;
Reviewed-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</content>
</entry>
<entry>
<title>board: lx2160aqds: add support for SerDes protocol 14</title>
<updated>2019-09-12T10:45:42Z</updated>
<author>
<name>Florin Chiculita</name>
<email>florinlaurentiu.chiculita@nxp.com</email>
</author>
<published>2019-08-26T07:48:20Z</published>
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<id>urn:sha1:b9fe1a261a0b32913384212fee33f73a5a42b406</id>
<content type='text'>
Add SerDes1 protocol 14 in the list of supported protocols.
This configuration enables one high-speed 100G port and PCIe x4.

Signed-off-by: Florin Chiculita &lt;florinlaurentiu.chiculita@nxp.com&gt;
Reviewed-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</content>
</entry>
<entry>
<title>board: lx2160aqds: fix ethernet-phy compatible property</title>
<updated>2019-09-12T10:45:42Z</updated>
<author>
<name>Florin Chiculita</name>
<email>florinlaurentiu.chiculita@nxp.com</email>
</author>
<published>2019-08-19T15:56:46Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=065ccdc710c80d24fcaf2ed947143bae075f8d7f'/>
<id>urn:sha1:065ccdc710c80d24fcaf2ed947143bae075f8d7f</id>
<content type='text'>
The code that generates the compatible property concatenates the
ethernet phy id and clause-compatible information without
separating them with a comma, resulting into no ethernet phy driver
getting loaded by Linux kernel.
Suffix phy_id_compatible_str with comma to fix this

Signed-off-by: Florin Chiculita &lt;florinlaurentiu.chiculita@nxp.com&gt;
Signed-off-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</content>
</entry>
<entry>
<title>board: fsl: lx2160a: implement board_fix_fdt</title>
<updated>2019-09-12T10:45:42Z</updated>
<author>
<name>Pankaj Bansal</name>
<email>pankaj.bansal@nxp.com</email>
</author>
<published>2019-08-17T01:07:32Z</published>
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<id>urn:sha1:5d535aa40bb73f248d307a2cfc58e6187465036d</id>
<content type='text'>
lx2160a rev1 and rev2 SoC has different pcie controller.
The pcie controller device tree node fields "compatible"
and registers names needs to be updated accordingly

This change in device tree is handled as part of
fdt fixups. These changes would only be applied
if the soc revision is not rev1.

Signed-off-by: Pankaj Bansal &lt;pankaj.bansal@nxp.com&gt;
Signed-off-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</content>
</entry>
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