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<title>u-boot.git/board, branch v2022.04</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/board?h=v2022.04</id>
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<updated>2022-03-31T17:06:16Z</updated>
<entry>
<title>qemu: arm: Remove platform specific function to get RNG device</title>
<updated>2022-03-31T17:06:16Z</updated>
<author>
<name>Sughosh Ganu</name>
<email>sughosh.ganu@linaro.org</email>
</author>
<published>2022-03-13T14:47:58Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=64437a05d255128392177984563e6a2128636834'/>
<id>urn:sha1:64437a05d255128392177984563e6a2128636834</id>
<content type='text'>
The QEMU platform has a function defined to get the random number
generator(RNG) device. However, the RNG device can be obtained simply
by searching for a device belonging to the RNG uclass. Remove the
superfluous platform function defined for the QEMU platform for
getting the RNG device.

Signed-off-by: Sughosh Ganu &lt;sughosh.ganu@linaro.org&gt;
Tested-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
Reviewed-by: Ilias Apalodimas &lt;ilias.apalodimas@linaro.org&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>board: gateworks: venice: determine dram size at runtime</title>
<updated>2022-03-31T12:27:52Z</updated>
<author>
<name>Tim Harvey</name>
<email>tharvey@gateworks.com</email>
</author>
<published>2022-03-30T20:39:02Z</published>
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<id>urn:sha1:52ae8d6cc8b2f4ec53228e1d9216b5d9071cb325</id>
<content type='text'>
The SPL does not update the memory node with the dram size from EEPROM
but instead we can use get_ram_size which does a simple memory test
to determine the available RAM. Update PHYS_SDRAM_SIZE to 4GiB as that
is the max used on the Venice boards.

Signed-off-by: Tim Harvey &lt;tharvey@gateworks.com&gt;
Reviewed-by: Fabio Estevam &lt;festevam@denx.de&gt;
</content>
</entry>
<entry>
<title>board: gw_ventana: gsc: fix GSC read/write functions</title>
<updated>2022-03-31T12:27:51Z</updated>
<author>
<name>Tim Harvey</name>
<email>tharvey@gateworks.com</email>
</author>
<published>2022-03-24T15:32:00Z</published>
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<id>urn:sha1:051df08fe072c3790c159d7b9966513325eb04ec</id>
<content type='text'>
commit 7c84319af9c7 ("dm: gpio: Correct use of -ENODEV in drivers")
changed the return code for an I2C NAK from -ENODEV to -EREMOTEIO.

Update the gsc_i2c_read and gsc_i2c_write functions for this change
to properly retry the transaction on a NAK meaning the GSC is busy.

Fixes: 7c84319af9c7 ("dm: gpio: Correct use of -ENODEV in drivers")
Signed-off-by: Tim Harvey &lt;tharvey@gateworks.com&gt;
Reviewed-by: Fabio Estevam &lt;festevam@denx.de&gt;
</content>
</entry>
<entry>
<title>sunxi: Fix old GMAC pinmux setup</title>
<updated>2022-03-26T00:16:06Z</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2022-03-15T00:00:53Z</published>
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<id>urn:sha1:e943753dc2e3cc10669f1b38ad068eaa0ba77731</id>
<content type='text'>
Commit 5bc4cd05d7d4 ("sunxi: move non-essential code out of s_init()")
moved the call to eth_init_board() from s_init() into board_init_f().
This means it's now only called from the SPL, which makes sense for
most of the other moved low-level functions. However the GMAC pinmux and
clock setup in eth_init_board() was not happy about that, so it broke
the sun7i GMAC.

Since Ethernet is of no use in the SPL anyway, just move the call into
board_init(), which is only run in U-Boot proper.

This fixes Ethernet operation for the A20 SoCs, which broke in
v2022.04-rc1, with the above mentioned commit.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Reviewed-by: Jernej Skrabec &lt;jernej.skrabec@gmail.com&gt;
Tested-by: Petr Štetiar &lt;ynezz@true.cz&gt; [a20-olinuxino-lime2]
</content>
</entry>
<entry>
<title>rockchip: rk3399: Add support for chromebook_kevin</title>
<updated>2022-03-18T10:12:03Z</updated>
<author>
<name>Marty E. Plummer</name>
<email>hanetzer@startmail.com</email>
</author>
<published>2021-12-24T13:43:46Z</published>
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<id>urn:sha1:6d36e92d28c9d009c786e29623c9558b7652ceda</id>
<content type='text'>
Add support for Kevin, an RK3399-based convertible chromebook that is
very similar to Bob. This patch is mostly based on existing support for
Bob, with only minor changes for Kevin-specific things.

Unlike other Gru boards, coreboot sets Kevin's center logic to 925 mV,
so adjust it here in the dts as well. The rk3399-gru-kevin devicetree
has an unknown event code reference which has to be defined, set it
to the Linux counterpart. The new defconfig is copied from Bob with the
diffconfig:

     DEFAULT_DEVICE_TREE "rk3399-gru-bob" -&gt; "rk3399-gru-kevin"
     DEFAULT_FDT_FILE "rockchip/rk3399-gru-bob.dtb" -&gt; "rockchip/rk3399-gru-kevin.dtb"
     VIDEO_ROCKCHIP_MAX_XRES 1280 -&gt; 2400
     VIDEO_ROCKCHIP_MAX_YRES 800 -&gt; 1600
    +TARGET_CHROMEBOOK_KEVIN y

With this Kevin can boot from SPI flash to a usable U-Boot prompt on the
display with the keyboard working, but cannot boot into Linux for
unknown reasons.

eMMC starts in a working state but fails to re-init, microSD card works
but at a lower-than-expected speed, USB works but causes a hang on
de-init. There are known workarounds to solve eMMC and USB issues.

Cc: Marty E. Plummer &lt;hanetzer@startmail.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
[Alper: commit message, resync config with Bob, update MAINTAINERS,
        add to Rockchip doc, add Kconfig help message, set regulator]
Co-developed-by: Alper Nebi Yasak &lt;alpernebiyasak@gmail.com&gt;
Signed-off-by: Alper Nebi Yasak &lt;alpernebiyasak@gmail.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>rockchip: gru: Set up SoC IO domain registers</title>
<updated>2022-03-18T10:12:03Z</updated>
<author>
<name>Alper Nebi Yasak</name>
<email>alpernebiyasak@gmail.com</email>
</author>
<published>2021-12-24T13:43:43Z</published>
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<id>urn:sha1:eb0ca6b5ecd8fbbbd55ebdf63a4a622fd6ec907f</id>
<content type='text'>
The RK3399 SoC needs to know the voltage value provided by some
regulators, which is done by setting relevant register bits. Configure
these the way other RK3399 boards do, but with the same values as are
set in the equivalent code in coreboot.

Signed-off-by: Alper Nebi Yasak &lt;alpernebiyasak@gmail.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>Merge https://source.denx.de/u-boot/custodians/u-boot-riscv</title>
<updated>2022-03-16T12:11:53Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2022-03-16T12:11:53Z</published>
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<id>urn:sha1:469c1bc688a1f607dea477ad1e7b2a067166d268</id>
<content type='text'>
- k210 updates
</content>
</entry>
<entry>
<title>Merge tag 'u-boot-stm32-20220315' of https://source.denx.de/u-boot/custodians/u-boot-stm</title>
<updated>2022-03-15T12:42:36Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2022-03-15T12:42:36Z</published>
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<id>urn:sha1:ababaa4a275b473bb4463b70d93e8faeebb24698</id>
<content type='text'>
mtd: add NAND write protect support to stm32_fmc2_nand
stm32mp1 bsec: Add permanent lock write support
stm32mp1 bsec: Add dev in function description
cmd_stboard: Update test on misc_read() result
video: fix the check of return value of clk_set_rate in stm32_ltdc
DT: Alignment with kernel v5.17 for stm32mp15
DT: Add USB OTG pinctrl and regulator in SPL for DHCOR
DT: Move vdd_io extras into Avenger96 extras
DT: Add DFU support for DHCOM recovery
ram: stm32mp1: Unconditionally enable ASR
psci: Implement PSCI system suspend and DRAM SSR for stm32mp
</content>
</entry>
<entry>
<title>k210: use the board vendor name rather than the marketing name</title>
<updated>2022-03-15T09:43:11Z</updated>
<author>
<name>Damien Le Moal</name>
<email>damien.lemoal@opensource.wdc.com</email>
</author>
<published>2022-03-01T10:35:39Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=fd426b31066ba61ee1ff96a2b56c919251ffdd9e'/>
<id>urn:sha1:fd426b31066ba61ee1ff96a2b56c919251ffdd9e</id>
<content type='text'>
"kendryte" is the marketing name for the K210 RISC-V SoC produced by
Canaan Inc. Rather than "kendryte,k210", use the usual "canaan,k210"
vendor,SoC compatibility string format in the device tree files and
use the SoC name for file names.
With these changes, the device tree files are more in sync with the
Linux kernel DTS and drivers, making uboot device tree usable by the
kernel.

Signed-off-by: Damien Le Moal &lt;damien.lemoal@opensource.wdc.com&gt;
Signed-off-by: Niklas Cassel &lt;niklas.cassel@wdc.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</content>
</entry>
<entry>
<title>board: st: common: update test on misc_read result in command stboard</title>
<updated>2022-03-15T08:10:52Z</updated>
<author>
<name>Patrick Delaunay</name>
<email>patrick.delaunay@foss.st.com</email>
</author>
<published>2022-02-01T13:37:19Z</published>
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<id>urn:sha1:6ed21f3d704370d5b1a5db8ee953fd7c5cea08d6</id>
<content type='text'>
Update management of misc_read/misc_write, which now returns length of
data after the commit 8729b1ae2cbd ("misc: Update read() and write()
methods to return bytes xfered"): raise a error when the result is not
the expected length.

Fixes: 658fde8a36ff ("board: stm32mp1: stboard: lock the OTP after programming")
Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@foss.st.com&gt;
Reviewed-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
</content>
</entry>
</feed>
