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<title>u-boot.git/cmd/riscv/exception.c, branch v2024.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
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<updated>2024-03-02T17:26:19Z</updated>
<entry>
<title>cmd: remove common.h from exception command implementations</title>
<updated>2024-03-02T17:26:19Z</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>heinrich.schuchardt@canonical.com</email>
</author>
<published>2024-02-12T16:53:29Z</published>
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<id>urn:sha1:9a49f393e4d3f4e83a75bf51e8fd49a3fb615d7b</id>
<content type='text'>
The common.h should not be used anymore.

Signed-off-by: Heinrich Schuchardt &lt;heinrich.schuchardt@canonical.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>cmd/exception: test RISC-V 16 bit aligned instruction</title>
<updated>2023-10-04T09:59:43Z</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>heinrich.schuchardt@canonical.com</email>
</author>
<published>2023-09-21T10:39:29Z</published>
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<id>urn:sha1:ef5ccaae64b670bc3183e20378d1fa31c86c9f44</id>
<content type='text'>
A 16 bit aligned instruction should generated an exception if the C
extension is not available.

Provide an 'extension ialign16' command for testing exception handling.

For testing build qemu-riscv64_defconfig with CONFIG_RISCV_ISA_C=n
and run with

    qemu-system-riscv64 -M virt -bios u-boot -nographic -cpu rv64,c=false

    =&gt; exception ialign16
    Unhandled exception: Instruction address misaligned
    EPC: 0000000087719138 RA: 0000000087719218 TVAL: 000000008771913e
    EPC: 0000000080020138 RA: 0000000080020218 reloc adjusted

    Code: 0113 0101 8067 0000 0113 ff01 3423 0011 (006f 0060)

Signed-off-by: Heinrich Schuchardt &lt;heinrich.schuchardt@canonical.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</content>
</entry>
<entry>
<title>cmd/exception: support RISC-V compressed instruction</title>
<updated>2023-10-04T09:59:40Z</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>heinrich.schuchardt@canonical.com</email>
</author>
<published>2023-09-21T08:42:18Z</published>
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<id>urn:sha1:f2e4b9d3c2f858f5ce7e317b2974d74353abb2a2</id>
<content type='text'>
Eliminating the C extension on application processors is under
discussion.

Support emitting a compressed instruction. This will lead to an
illegal instruction exception if the C extension is not implemented.

For testing build qemu-riscv64_defconfig with CONFIG_RISCV_ISA_C=n
and run with

    qemu-system-riscv64 -M virt -bios u-boot -nographic -cpu rv64,c=false

    =&gt; exception compressed
    Unhandled exception: Illegal instruction
    EPC: 0000000087731708 RA: 000000008773fe44 TVAL: 0000000000004501
    EPC: 000000008001b708 RA: 0000000080029e44 reloc adjusted

    Code: 0b93 0000 0493 0000 0993 0000 f06f ccdf (4501)

Signed-off-by: Heinrich Schuchardt &lt;heinrich.schuchardt@canonical.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</content>
</entry>
<entry>
<title>cmd/exception: support ebreak exception on RISC-V</title>
<updated>2021-05-05T08:13:12Z</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>xypron.glpk@gmx.de</email>
</author>
<published>2021-04-09T10:48:14Z</published>
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<id>urn:sha1:91e4b7516d84cefab7324765b3c8d6a909185ce2</id>
<content type='text'>
The ebreak instruction should generate a breakpoint exception.

Signed-off-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
</content>
</entry>
<entry>
<title>cmd: exception: unaligned data access on RISC-V</title>
<updated>2020-08-14T06:39:34Z</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>xypron.glpk@gmx.de</email>
</author>
<published>2020-08-06T10:34:59Z</published>
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<id>urn:sha1:db3585d181221dd025fcdece9d56b02da63cfe96</id>
<content type='text'>
The command 'exception' can be used to test the handling of exceptions.

Currently the exception command only allows to create an illegal
instruction exception on RISC-V.

Provide a sub-command 'exception unaligned' to cause a misaligned load
address exception.

Adjust the online help for 'exception undefined'.

Signed-off-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
</content>
</entry>
<entry>
<title>command: Remove the cmd_tbl_t typedef</title>
<updated>2020-05-18T22:36:55Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-05-10T17:40:03Z</published>
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<id>urn:sha1:09140113108541b95d340f3c7b6ee597d31ccc73</id>
<content type='text'>
We should not use typedefs in U-Boot. They cannot be used as forward
declarations which means that header files must include the full header to
access them.

Drop the typedef and rename the struct to remove the _s suffix which is
now not useful.

This requires quite a few header-file additions.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>cmd: add exception command</title>
<updated>2019-04-22T16:06:39Z</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>xypron.glpk@gmx.de</email>
</author>
<published>2018-12-26T16:20:35Z</published>
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<id>urn:sha1:dab8788a8cadaa18a44001f98fa959fc672fff4f</id>
<content type='text'>
The 'exception' command allows to test exception handling.

This implementation supports ARM, x86, RISC-V and the following exceptions:
* 'breakpoint' - prefetch abort exception (ARM 32bit only)
* 'unaligned'  - data abort exception (ARM only)
* 'undefined'  - undefined instruction exception

Signed-off-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
</content>
</entry>
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