u-boot.git/cmd/riscv, branch v2024.04

cmd: sbi: formatting PolarFire Hart Software Services version

2024-03-12T06:36:13Z

The 'PolarFire Hart Software Services' SBI implementation returns the version of the incorporated OpenSBI. Format the number accordingly. Signed-off-by: Heinrich Schuchardt Reviewed-by: Conor Dooley

cmd: sbi: Correctly display unknown implementation IDs

2024-03-12T06:36:13Z

For an unknown implementation ID an output like SBI 1.0Unknown implementation ID 16777216 Extensions: sbi_set_timer ... was shown. The number 16777216 is not the implementation ID. * Show the correct number * Use a hexadecimal output format * Add a missing line feed Signed-off-by: Heinrich Schuchardt Reviewed-by: Conor Dooley Reviewed-by: Dan Carpenter

cmd: sbi: add support for Debug Trigger Extension

2024-01-31T08:52:30Z

Detect and show if the SBI implements the Debug Trigger Extension. Signed-off-by: Heinrich Schuchardt Reviewed-by: Leo Yu-Chi Liang

cmd: Convert existing long help messages to the new macro

2023-10-16T14:24:58Z

- Generally we just drop the #ifdef CONFIG_SYS_LONGHELP and endif lines and use U_BOOT_LONGHELP to declare the same variable name as before - In a few places, either rename the variable to follow convention or introduce the variable as it was being done inline before. Signed-off-by: Tom Rini Reviewed-by: Simon Glass

cmd/exception: test RISC-V 16 bit aligned instruction

2023-10-04T09:59:43Z

A 16 bit aligned instruction should generated an exception if the C extension is not available. Provide an 'extension ialign16' command for testing exception handling. For testing build qemu-riscv64_defconfig with CONFIG_RISCV_ISA_C=n and run with qemu-system-riscv64 -M virt -bios u-boot -nographic -cpu rv64,c=false => exception ialign16 Unhandled exception: Instruction address misaligned EPC: 0000000087719138 RA: 0000000087719218 TVAL: 000000008771913e EPC: 0000000080020138 RA: 0000000080020218 reloc adjusted Code: 0113 0101 8067 0000 0113 ff01 3423 0011 (006f 0060) Signed-off-by: Heinrich Schuchardt Reviewed-by: Leo Yu-Chi Liang

cmd/exception: support RISC-V compressed instruction

2023-10-04T09:59:40Z

Eliminating the C extension on application processors is under discussion. Support emitting a compressed instruction. This will lead to an illegal instruction exception if the C extension is not implemented. For testing build qemu-riscv64_defconfig with CONFIG_RISCV_ISA_C=n and run with qemu-system-riscv64 -M virt -bios u-boot -nographic -cpu rv64,c=false => exception compressed Unhandled exception: Illegal instruction EPC: 0000000087731708 RA: 000000008773fe44 TVAL: 0000000000004501 EPC: 000000008001b708 RA: 0000000080029e44 reloc adjusted Code: 0b93 0000 0493 0000 0993 0000 f06f ccdf (4501) Signed-off-by: Heinrich Schuchardt Reviewed-by: Leo Yu-Chi Liang

cmd/sbi: display new extensions

2023-08-10T02:57:56Z

The SBI specification v2.0-rc2 defines new extensions: * Nested Acceleration Extension (NACL) * Steal Time Accounting (STA) Allow the sbi command to display these. Add missing implementation IDs. Signed-off-by: Heinrich Schuchardt Reviewed-by: Leo Yu-Chi Liang

cmd/sbi: display new extensions

2023-07-06T09:28:08Z

OpenSBI already implements some extensions that are not ratified yet: * Debug Console Extension (DBCN) * System Suspend Extension (SUSP) * Collaborative Processor Performance Control Extension (CPPC) Allow the sbi command to display these. Provide the FID definitions of the Debug Console Extension. We can use that extension for an early debug console driver. Signed-off-by: Heinrich Schuchardt Reviewed-by: Leo Yu-Chi Liang

cmd/sbi: user friendly short texts

2022-10-20T07:22:15Z

In the sbi command use the same short texts for the legacy extensions as the SBI specification 1.0.0. Signed-off-by: Heinrich Schuchardt Reviewed-by: Rick Chen

cmd/sbi: error message for failure to get spec version

2022-10-20T07:22:15Z

If calling 'Get SBI specification version' fails, write an error message and return CMD_RET_FAILURE. Signed-off-by: Heinrich Schuchardt Reviewed-by: Rick Chen