treewide: move bi_dram[] from bd to gd

2026-06-25T00:13:24Z

Currently, the bi_dram[] information is stored in the board info structure (bd). Because bd is only valid after reserve_board(), dram_init_banksize() must be called late in the initialization process. This limitation is problematic, as it forces us to rely on a variety of bespoke functions to determine board RAM, bank memory sizes, and other early setup requirements. By moving bi_dram[] into the global data (gd), we can run it earlier. This is particularly convenient since boards define their own dram_init_banksize() routines, which do not always rely on parsing Device Tree (DT) memory nodes. Additionally, U-Boot defaults to relocating to the top of the first memory bank. While boards currently use custom functions to override this behavior, having the DRAM bank information available earlier in gd makes relocating to a different bank trivial and standardizes the process. Reviewed-by: Anshul Dalal Tested-by: Michal Simek # Versal Gen 2 Vek385 Tested-by: Anshul Dalal Reviewed-by: Simon Glass Signed-off-by: Ilias Apalodimas Tested-by: Christophe Leroy (CS GROUP)

cmd: ti: Add DDRSS Inline ECC Error Injection command

2025-10-15T21:08:27Z

Introduce a new version of the Keystone-II "ddr" command for testing the inline ECC support in the DDRSS bridge available on K3 devices. The ECC hardware support in K3's DDRSS and the test method differ substantially from what we support in the K2 variant of the command. This K3 DDRSS command currently supports only single controller testing. The ECC error injection procedure follows these steps: 1) Flush and disable the data cache. 2) Disable the protected ECC Rx range. 3) Flip a bit in the address. 4) Restore the range to original. 5) Read the modified value (corrected). 6) Re-enable the data cache. This will cause the 1-bit ECC error count to increase while the read will return the corrected value. The K3 version of the command extends the syntax for the "ecc_err" argument by also introducing an argument for range which specifies which range (0, 1, 2) the address is located in. Multi-bit ECC errors are uncorrectable and will lead to a synchronous abort. Signed-off-by: Georgi Vlaev Signed-off-by: Santhosh Kumar K [n-francis@ti.com: Add J7 and multiple-region support, simplify logic] Signed-off-by: Neha Malcom Francis Reviewed-by: Udit Kumar

u-boot.git/cmd/ti/ddr4.c, branch main

treewide: move bi_dram[] from bd to gd

cmd: ti: Add DDRSS Inline ECC Error Injection command