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<title>u-boot.git/common/spl/Kconfig, branch v2020.04</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/common/spl/Kconfig?h=v2020.04</id>
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<updated>2020-01-24T17:36:56Z</updated>
<entry>
<title>sunxi: move CONFIG_SYS_SPI_U_BOOT_OFFS out of defconfig</title>
<updated>2020-01-24T17:36:56Z</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2020-01-06T01:29:10Z</published>
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<id>urn:sha1:671d64fe352244374e8aa27186e7b8055446cb6b</id>
<content type='text'>
For Allwinner SoCs the CONFIG_SYS_SPI_U_BOOT_OFFS value is not really a
board choice: The boot ROM only loads the SPL from offset 0 of the SPI
NOR flash, and loads at most 32KB. This is a similar situation as on MMC,
so consequently we create our "joint" image (SPL + U-Boot proper) with
that 32KB offset during the build.

So define the value of this symbol to be 32KB by default for every
Allwinner SoC. This removes the definition of this symbol from the
_defconfig files, and avoids every board to define this over and over
again.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell</title>
<updated>2020-01-16T17:52:07Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2020-01-16T17:52:07Z</published>
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<id>urn:sha1:994bb86fc90aa9edff5a6685b28b44e2f77de196</id>
<content type='text'>
- Clearfog: Fix SD booting (Baruch)
- Misc updates to MMC handling in SPL to support booting from
  main data partition (vs hardware boot partition) on MVEBU (Baruch)
</content>
</entry>
<entry>
<title>spl: mmc: support uboot image offset on main partition</title>
<updated>2020-01-16T09:58:52Z</updated>
<author>
<name>Baruch Siach</name>
<email>baruch@tkos.co.il</email>
</author>
<published>2020-01-15T07:08:08Z</published>
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<id>urn:sha1:e42afd8416fea64725eddf26be4ec3a0397778d6</id>
<content type='text'>
On Armada 38x platforms the ROM code loads SPL from offset 0 of eMMC
hardware boot partitions. When there are no boot partitions (i.e. SD
card) the ROM skips the first sector that usually contains the (logical)
partition table. Since the generated .kwb image contains the main U-Boot
image in a fixed location (0x140 sectors by default), we end up with the
main U-Boot image in offset of 1 sector. The current workaround is to
manually set CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR to 0x141 to
compensate for that.

This patch uses the run-time detected boot partition to determine the
right offset of the main U-Boot partition. The generated .kwb image is
now compatible with both eMMC boot partition, and SD card main data
partition.

Signed-off-by: Baruch Siach &lt;baruch@tkos.co.il&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>Kconfig: Rename CONFIG_SPL_DMA_SUPPORT to CONFIG_SPL_DMA</title>
<updated>2020-01-16T00:50:27Z</updated>
<author>
<name>Vignesh Raghavendra</name>
<email>vigneshr@ti.com</email>
</author>
<published>2019-11-15T11:30:41Z</published>
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<id>urn:sha1:74326a320a93e8c2596223545bcb14702e8b87ac</id>
<content type='text'>
Rename CONFIG_SPL_DMA_SUPPORT to CONFIG_SPL_DMA. This allows to use
macros such as CONFIG_IS_ENABLED() that allow conditional compilation of
code for SPL and U-Boot.

Signed-off-by: Vignesh Raghavendra &lt;vigneshr@ti.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>spl: Allow cache drivers to be used in SPL</title>
<updated>2020-01-07T13:38:33Z</updated>
<author>
<name>Ley Foon Tan</name>
<email>ley.foon.tan@intel.com</email>
</author>
<published>2019-10-11T05:48:33Z</published>
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<id>urn:sha1:5c9c71b660a01d088ac66b7b8c1378915bcef68e</id>
<content type='text'>
Add an option for building cache drivers in SPL.

Signed-off-by: Ley Foon Tan &lt;ley.foon.tan@intel.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Simon Goldschmidt &lt;simon.k.r.goldschmidt@gmail.com&gt;
</content>
</entry>
<entry>
<title>configs: Enable SPL_FSL_PBL for some LayerScape platforms</title>
<updated>2019-12-26T10:30:20Z</updated>
<author>
<name>Alison Wang</name>
<email>alison.wang@nxp.com</email>
</author>
<published>2019-12-04T06:21:55Z</published>
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<id>urn:sha1:5d168adf2b8babecc863d5d390bfc9953648040a</id>
<content type='text'>
In commit &lt;db4080d56dec&gt;, SPL_FSL_PBL is removed from the configs of
some LayerScape platforms. Actually, SPL_FSL_PBL is needed for SD/NAND
boot on LS1021A/LS1043A/LS1046A to create boot binary having SPL binary
in PBI format concatenated with u-boot binary. SPL_FRAMEWORK is used on
these platforms too.

Signed-off-by: Alison Wang &lt;alison.wang@nxp.com&gt;
Reviewed-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</content>
</entry>
<entry>
<title>spl: cache: Allow cache drivers in SPL</title>
<updated>2019-12-10T00:23:10Z</updated>
<author>
<name>Rick Chen</name>
<email>rick@andestech.com</email>
</author>
<published>2019-11-14T05:52:26Z</published>
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<id>urn:sha1:31dae22faa65534cb71631f6c74cbdcf4930a339</id>
<content type='text'>
When ax25-ae350 try to enable v5l2 cache
driver in SPL configuration, it need this
option for cache support in SPL.

Signed-off-by: Rick Chen &lt;rick@andestech.com&gt;
Cc: KC Lin &lt;kclin@andestech.com&gt;
Cc: Alan Kao &lt;alankao@andestech.com&gt;
</content>
</entry>
<entry>
<title>spl: Introduce SPL_DM_GPIO Kconfig define</title>
<updated>2019-12-05T15:28:38Z</updated>
<author>
<name>Lukasz Majewski</name>
<email>lukma@denx.de</email>
</author>
<published>2019-12-02T09:24:16Z</published>
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<id>urn:sha1:d4d65e1125459c8e8286684c8e84fdc7df9da062</id>
<content type='text'>
This define indicates if DM_GPIO shall be supported in SPL. This allows
proper operation of DM converted GPIO drivers in SPL, which use
boards.

Signed-off-by: Lukasz Majewski &lt;lukma@denx.de&gt;
</content>
</entry>
<entry>
<title>cosmetic: Fix spelling and whitespace errors</title>
<updated>2019-12-03T13:43:23Z</updated>
<author>
<name>Thomas Hebb</name>
<email>tommyhebb@gmail.com</email>
</author>
<published>2019-11-14T02:18:03Z</published>
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<id>urn:sha1:32f2ca2a7e2ec3ecd0cfd56faebf4003001226fd</id>
<content type='text'>
Signed-off-by: Thomas Hebb &lt;tommyhebb@gmail.com&gt;
</content>
</entry>
<entry>
<title>spl: separate SPL_FRAMEWORK config for spl and tpl</title>
<updated>2019-11-17T09:22:53Z</updated>
<author>
<name>Heiko Stuebner</name>
<email>heiko.stuebner@theobroma-systems.com</email>
</author>
<published>2019-07-16T08:12:02Z</published>
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<id>urn:sha1:22b7b860051d3f18cfd3bb9750b907174b3eee2b</id>
<content type='text'>
Right now enabling SPL_FRAMEWORK will also enable it for the TPL in all
cases, making the TPL bigger. There may be cases where the TPL is really
size constrained due to its underlying ram size.

Therefore introduce a new TPL_FRAMEWORK option and make the relevant
conditionals check for both. The default is set to "y if SPL_FRAMEWORK"
to mimic the previous behaviour where the TPL would always get the
SPL framework if it was enabled in SPL.

Signed-off-by: Heiko Stuebner &lt;heiko.stuebner@theobroma-systems.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
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