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<title>u-boot.git/common/spl/Kconfig, branch v2024.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/common/spl/Kconfig?h=v2024.01</id>
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<updated>2023-12-06T23:08:37Z</updated>
<entry>
<title>sunxi: h616: (really) lower SPL stack address to avoid BROM data</title>
<updated>2023-12-06T23:08:37Z</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2022-07-13T15:27:57Z</published>
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<id>urn:sha1:0d8ac5644eaf774c52669921ac4152874c6fc4ca</id>
<content type='text'>
When using the USB OTG FEL mode on the Allwinner H616, the BootROM
stores some data at the end of SRAM C. This is also the location where
we place the initial SPL stack, so it will overwrite this data.
We still need the BROM code after running the SPL, so should leave that
area alone.
Interestingly this does not seem to have an adverse effect, I guess on
the "way out" (when we return to FEL after the SPL has run), this data
is not needed by the BROM, for just the trailing end of the USB operation.
However this is still wrong, and we should not clobber BROM data.

Lower the SPL stack address to be situated right below the swap buffers
we use in sunxi-fel: that should be out of the way of everyone else.

This obsoletes a previous commit (eb53e7743c8f) with the same name:
that one was changing the address in an *unused* macro in sunxi_common.h,
so the previous patch didn't have any effect at all.

Fixes: eb53e7743c8f ("sunxi: h616: lower SPL stack address to avoid BROM data")
Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
</entry>
<entry>
<title>sunxi: add Allwinner R528/T113 SoC support</title>
<updated>2023-10-22T22:41:52Z</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2022-09-06T14:59:57Z</published>
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<id>urn:sha1:95168d77d391b1464af9f99ca44a2e46f309c32e</id>
<content type='text'>
This adds the remaining code bits to teach U-Boot about Allwinner's
newest SoC generation. This was introduced with the RISC-V based
Allwinner D1 SoC, which actually shares a die with the ARM cores versions
called R528 (BGA, without DRAM) and T113s (QFP, with embedded DRAM).

This adds the new Kconfig stanza, using the two newly introduced symbols
for the new SoC generation and pincontroller. It also adds the new symbols
to the relavent code places, to set all the hardcoded bits directly.

We need one DT override:
The ARM core version of the DT specifies the CPUX watchdog as
"reserved", which means it won't be recognised by U-Boot. Override this
in our generic sunxi-u-boot.dtsi, to let U-Boot pick up this watchdog,
so that the generic reset driver will work.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
</entry>
<entry>
<title>sunxi: introduce NCAT2 generation model</title>
<updated>2023-10-22T22:41:46Z</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2022-10-05T16:54:19Z</published>
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<id>urn:sha1:4a9e89a3e390bbff31aec25f9ec6d32e29e355f5</id>
<content type='text'>
Allwinner seems to typically stick to a common MMIO memory map for
several SoCs, but from time to time does some breaking changes, which
also introduce new generations of some peripherals. The last time this
happened with the H6, which apart from re-organising the base addresses
also changed the clock controller significantly. We added a
CONFIG_SUN50I_GEN_H6 symbol back then to mark SoCs sharing those traits.

Now the Allwinner D1 changes the memory map again, and also extends the
pincontroller, among other peripherals.
To mark this generation of SoCs, add a CONFIG_SUNXI_GEN_NCAT2 symbol,
this name is reportedly used in the Allwinner BSP code, and prevents us
from inventing our own name.

Add this new symbol to some guards that were already checking for the H6
generation, since many features are shared between the two (like the
renovated clock controller).

This paves the way to introduce a first user of this generation.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Tested-by: Samuel Holland &lt;samuel@sholland.org&gt;
</content>
</entry>
<entry>
<title>fs: ext4: Fix building ext4 in SPL if write is enabled</title>
<updated>2023-10-18T00:50:52Z</updated>
<author>
<name>Sean Anderson</name>
<email>seanga2@gmail.com</email>
</author>
<published>2023-10-14T20:47:49Z</published>
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<id>urn:sha1:44071cd5a8b1719397fe818d1c6ebc67a5db1953</id>
<content type='text'>
If EXT4_WRITE is enabled, write capabilities will be compiled into SPL, but
not CRC16. Add an option to enable CRC16 to avoid linker errors.

Signed-off-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>Move i.MX8 container image loading support to common/spl</title>
<updated>2023-10-18T00:50:52Z</updated>
<author>
<name>Sean Anderson</name>
<email>seanga2@gmail.com</email>
</author>
<published>2023-10-14T20:47:45Z</published>
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<id>urn:sha1:12b3339070bcab746355647a6aae7498f28c4add</id>
<content type='text'>
To facilitate testing loading i.MX8 container images, move the
parse-container code to common/spl.

Signed-off-by: Sean Anderson &lt;seanga2@gmail.com&gt;
</content>
</entry>
<entry>
<title>spl: Rename SYS_SPL_ARGS_ADDR to SPL_PAYLOAD_ARGS_ADDR</title>
<updated>2023-10-06T18:38:11Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2023-09-26T14:14:17Z</published>
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<id>urn:sha1:9cbdc3a0fca805bb1fd9ccf85114c504860814b9</id>
<content type='text'>
Rename this so that SPL is first, as per U-Boot convention. Also add
PAYLOAD_ since this is where in memory the parameters for the payload
have been stored.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>spl: Use CONFIG_SPL... instead of CONFIG_..._SPL_...</title>
<updated>2023-10-06T18:38:11Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2023-09-26T14:14:16Z</published>
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<id>urn:sha1:82e26e0d6883673bdedbcdb0ddd4bc967ce6ce70</id>
<content type='text'>
We like to put the SPL first so it is clear that it relates to SPL. Rename
various malloc-related options which have crept in, to stick to this
convention.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Marcel Ziswiler &lt;marcel.ziswiler@toradex.com&gt;
Reviewed-by: Martyn Welch &lt;martyn.welch@collabora.com&gt;
Reviewed-by: Svyatoslav Ryhel &lt;clamor95@gmail.com&gt;
</content>
</entry>
<entry>
<title>Kconfigs: Correct default of "0" on hex type entries</title>
<updated>2023-08-09T13:21:42Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-08-02T15:09:43Z</published>
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<id>urn:sha1:a077ac13d03c8cde646ddab30b03ec0f8b753e1e</id>
<content type='text'>
It is not a parse error to have a default value of "0" for a "hex" type
entry, instead of "0x0".  However, "0" and "0x0" are not treated the
same even by the tools themselves. Correct this by changing the default
value from "0" to "0x0" for all hex type questions that had the
incorrect default. Fix one instance (in two configs) of a default of "0"
being used on a hex question to be "0x0". Remove the cases where a
defconfig had set a value of "0x0" to be used as the default had been
"0".

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>spl: move SPL_CRC32 option to lib/Kconfig</title>
<updated>2023-08-07T17:41:44Z</updated>
<author>
<name>Oleksandr Suvorov</name>
<email>oleksandr.suvorov@foundries.io</email>
</author>
<published>2023-08-03T16:05:40Z</published>
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<id>urn:sha1:af62d83cc0ee27ca5051718a0df44341f71abff1</id>
<content type='text'>
All SPL hash algorithm options are collected in lib/Kconfig. Move
SPL_CRC32 there as well.

Signed-off-by: Oleksandr Suvorov &lt;oleksandr.suvorov@foundries.io&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>spl: remove duplicate SPL_MD5 option</title>
<updated>2023-08-07T17:41:44Z</updated>
<author>
<name>Oleksandr Suvorov</name>
<email>oleksandr.suvorov@foundries.io</email>
</author>
<published>2023-08-03T16:05:39Z</published>
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<id>urn:sha1:0d2761abbde00e1ff756426fdb77b4b30192311d</id>
<content type='text'>
There is another SPL_MD5 option defined in lib/Kconfig.
Renaming SPL_MD5_SUPPORT introduced duplicate option with
different description. As for now FIT and hash algorithm options
are not related to each others, removing a duplicate option seems OK.

Fixes: 4b00fd1a84c ("Kconfig: Rename SPL_MD5_SUPPORT to SPL_MD5")
Signed-off-by: Oleksandr Suvorov &lt;oleksandr.suvorov@foundries.io&gt;
</content>
</entry>
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