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<title>u-boot.git/common/spl/Kconfig, branch v2024.04</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/common/spl/Kconfig?h=v2024.04</id>
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<updated>2024-02-04T10:01:03Z</updated>
<entry>
<title>spl: Make SPL_STACK available for ROCKCHIP_RK3036 without spl framework</title>
<updated>2024-02-04T10:01:03Z</updated>
<author>
<name>Kever Yang</name>
<email>kever.yang@rock-chips.com</email>
</author>
<published>2024-01-24T07:42:04Z</published>
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<id>urn:sha1:ce7ae9d2dbe1190153157bddfdefb121f09e1e3e</id>
<content type='text'>
rk3036 soc has limit internal sram, and not able to support spl
framework.

Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>spl: riscv: falcon: move fdt blob to specified address</title>
<updated>2024-01-31T08:51:03Z</updated>
<author>
<name>Randolph</name>
<email>randolph@andestech.com</email>
</author>
<published>2023-12-29T08:32:22Z</published>
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<id>urn:sha1:10c4ab898c251a9f8d79b525880a1751b4815350</id>
<content type='text'>
In Falcon Boot mode, the fdt blob should be move to the RAM from
kernel BSS section. To avoid being cleared by BSS initialisation.
SPL_PAYLOAD_ARGS_ADDR is the address where SPL copies.

Signed-off-by: Randolph &lt;randolph@andestech.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</content>
</entry>
<entry>
<title>sunxi: Consider SPL size limitations for FIT loading</title>
<updated>2024-01-29T14:31:00Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel@sholland.org</email>
</author>
<published>2023-10-31T05:17:41Z</published>
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<id>urn:sha1:539612e27690a8df7f197cd1e9f4c2cf6ee1ac64</id>
<content type='text'>
Now that 32-bit SoCs can load U-Boot proper (and possibly other firmware)
from a FIT, people can use that by enabling CONFIG_SPL_LOAD_FIT.
However SPL_FIT_IMAGE_TINY is required to stay within the 24 or 32 KiB
SPL size limit on early SoCs; for consistency, enable it everywhere.

Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
[Andre: drop unconditional FIT image enablement for all SoCs]
Reviewed-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
</entry>
<entry>
<title>sunxi: spl: Disable padding from SPL_PAD_TO</title>
<updated>2024-01-29T14:30:59Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel@sholland.org</email>
</author>
<published>2023-10-31T05:17:38Z</published>
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<id>urn:sha1:d72494a06443061f150742910e9441fe9c9e14f3</id>
<content type='text'>
Starting with H6, Allwinner removed the artificial 32 KiB SPL size limit
from the boot ROM. Now SPL size is only limited by the available SRAM.
This limit ranges from 152 KiB on H6 to a whopping 2052 KiB on R329. To
take advantage of this additional space, we must increase SPL_MAX_SIZE.
Since we do not want to unnecessarily pad SPL out to these giant sizes,
we must set SPL_PAD_TO to zero. This causes no problems because binman
already takes care of appending the SPL payload at the right offset.

Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
Reviewed-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
</entry>
<entry>
<title>spl: binman: Disable u_boot_any symbols for i.MX93 boards</title>
<updated>2024-01-08T17:37:50Z</updated>
<author>
<name>Mathieu Othacehe</name>
<email>m.othacehe@gmail.com</email>
</author>
<published>2023-12-29T10:59:29Z</published>
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<id>urn:sha1:da96f93cda90213f20cb81e484b03055d233a054</id>
<content type='text'>
This is extending commit 6516c9b349b3 ("spl: binman: Disable u_boot_any
symbols for i.MX8M boards") to i.MX93 boards.

Signed-off-by: Mathieu Othacehe &lt;m.othacehe@gmail.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'v2024.01-rc5' into next</title>
<updated>2023-12-18T14:55:32Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-12-18T13:31:50Z</published>
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<id>urn:sha1:1373ffde52e16af83fb14a1d228508a8caaa9996</id>
<content type='text'>
Prepare v2024.01-rc5
</content>
</entry>
<entry>
<title>sunxi: h616: (really) lower SPL stack address to avoid BROM data</title>
<updated>2023-12-06T23:08:37Z</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2022-07-13T15:27:57Z</published>
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<id>urn:sha1:0d8ac5644eaf774c52669921ac4152874c6fc4ca</id>
<content type='text'>
When using the USB OTG FEL mode on the Allwinner H616, the BootROM
stores some data at the end of SRAM C. This is also the location where
we place the initial SPL stack, so it will overwrite this data.
We still need the BROM code after running the SPL, so should leave that
area alone.
Interestingly this does not seem to have an adverse effect, I guess on
the "way out" (when we return to FEL after the SPL has run), this data
is not needed by the BROM, for just the trailing end of the USB operation.
However this is still wrong, and we should not clobber BROM data.

Lower the SPL stack address to be situated right below the swap buffers
we use in sunxi-fel: that should be out of the way of everyone else.

This obsoletes a previous commit (eb53e7743c8f) with the same name:
that one was changing the address in an *unused* macro in sunxi_common.h,
so the previous patch didn't have any effect at all.

Fixes: eb53e7743c8f ("sunxi: h616: lower SPL stack address to avoid BROM data")
Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
</entry>
<entry>
<title>spl: fat: Add option to disable DMA alignment</title>
<updated>2023-11-16T18:49:14Z</updated>
<author>
<name>Sean Anderson</name>
<email>seanga2@gmail.com</email>
</author>
<published>2023-11-08T16:48:58Z</published>
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<id>urn:sha1:54a8d845be4f236a5eb7c93d927ff16cb3efb5fe</id>
<content type='text'>
If we don't DMA-align buffers we pass to FAT, it will align them itself.
This behaviour likely should be deprecated in favor of
CONFIG_BOUNCE_BUFFER, but that's a task for another series. For the
meantime, don't bother aligning the buffer unless we had been doing so in
the past.

Signed-off-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>spl: Convert mmc to spl_load</title>
<updated>2023-11-16T18:49:14Z</updated>
<author>
<name>Sean Anderson</name>
<email>seanga2@gmail.com</email>
</author>
<published>2023-11-08T16:48:50Z</published>
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<id>urn:sha1:5d3401a448353767c5e67246a79271c9ee6f3f73</id>
<content type='text'>
This converts the mmc loader to spl_load. Legacy images are handled by
spl_load (via spl_parse_image_header), so mmc_load_legacy can be
omitted. To accurately determine whether mmc_load_image_raw_sector is used
(which might not be the case if SYS_MMCSD_FS_BOOT is enabled), we introduce
a helper config SYS_MMCSD_RAW_MODE. This ensures we can inline spl_load
correctly when a board only boots from filesystems. We still need to check
for SPL_MMC, since some boards enable configure raw mode even without MMC
support.

Signed-off-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>spl: Only support bl_len when we have to</title>
<updated>2023-11-16T18:49:14Z</updated>
<author>
<name>Sean Anderson</name>
<email>seanga2@gmail.com</email>
</author>
<published>2023-11-08T16:48:43Z</published>
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<id>urn:sha1:5271e359a46cc6a60d0048576326e2fa1527f231</id>
<content type='text'>
Aligning addresses and sizes causes overhead which is unnecessary when we
are not loading from block devices. Remove bl_len when it is not needed.

For example, on iot2050 we save 144 bytes with this patch (once the rest of
this series is applied):

add/remove: 0/0 grow/shrink: 0/3 up/down: 0/-144 (-144)
Function                                     old     new   delta
spl_load_simple_fit                          920     904     -16
load_simple_fit                              496     444     -52
spl_spi_load_image                           384     308     -76
Total: Before=87431, After=87287, chg -0.16%

We use panic() instead of BUILD_BUG_ON in spl_set_bl_len because we still
need to be able to compile it for things like mmc_load_image_raw_sector,
even if that function will not be used.

Signed-off-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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