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<title>u-boot.git/common/spl/spl_opensbi.c, branch v2020.10</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>riscv: Make SiFive HiFive Unleashed board boot again</title>
<updated>2020-07-24T06:55:04+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bin.meng@windriver.com</email>
</author>
<published>2020-07-20T06:17:07+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a0018fc8209c0bf7188592527fc0a7d459b9c144'/>
<id>a0018fc8209c0bf7188592527fc0a7d459b9c144</id>
<content type='text'>
Commit 40686c394e53 ("riscv: Clean up IPI initialization code")
caused U-Boot failed to boot on SiFive HiFive Unleashed board.

The codes inside arch_cpu_init_dm() may call U-Boot timer APIs
before the call to riscv_init_ipi(). At that time the timer register
base (e.g.: the SiFive CLINT device in this case) is unknown yet.

It might be the name riscv_init_ipi() that misleads people to only
consider it is related to IPI, but in fact the timer capability is
provided by the same SiFive CLINT device that provides the IPI.
Timer capability is needed for both UP and SMP.

Considering that the original refactor does have benefits, that it
makes the IPI code more similar to U-Boot initialization idioms.
It also removes some quite ugly macros. Let's do the minimal revert
instead of a complete revert, plus a fixes to arch_cpu_init_dm() to
consider the SPL case.

Fixes: 40686c394e53 ("riscv: Clean up IPI initialization code")
Signed-off-by: Bin Meng &lt;bin.meng@windriver.com&gt;
Reviewed-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Tested-by: Leo Liang &lt;ycliang@andestech.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Commit 40686c394e53 ("riscv: Clean up IPI initialization code")
caused U-Boot failed to boot on SiFive HiFive Unleashed board.

The codes inside arch_cpu_init_dm() may call U-Boot timer APIs
before the call to riscv_init_ipi(). At that time the timer register
base (e.g.: the SiFive CLINT device in this case) is unknown yet.

It might be the name riscv_init_ipi() that misleads people to only
consider it is related to IPI, but in fact the timer capability is
provided by the same SiFive CLINT device that provides the IPI.
Timer capability is needed for both UP and SMP.

Considering that the original refactor does have benefits, that it
makes the IPI code more similar to U-Boot initialization idioms.
It also removes some quite ugly macros. Let's do the minimal revert
instead of a complete revert, plus a fixes to arch_cpu_init_dm() to
consider the SPL case.

Fixes: 40686c394e53 ("riscv: Clean up IPI initialization code")
Signed-off-by: Bin Meng &lt;bin.meng@windriver.com&gt;
Reviewed-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Tested-by: Leo Liang &lt;ycliang@andestech.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'next'</title>
<updated>2020-07-06T19:46:38+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2020-07-06T19:46:38+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6e7d7aa2e2062995c1cbc3af81cf40c04c50ad30'/>
<id>6e7d7aa2e2062995c1cbc3af81cf40c04c50ad30</id>
<content type='text'>
Merge all outstanding changes from the current next branch in now that
we have released.
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Merge all outstanding changes from the current next branch in now that
we have released.
</pre>
</div>
</content>
</entry>
<entry>
<title>riscv: sbi: Add newline to error message</title>
<updated>2020-07-02T02:02:57+00:00</updated>
<author>
<name>Sean Anderson</name>
<email>seanga2@gmail.com</email>
</author>
<published>2020-06-06T19:26:03+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7984922fb252942534a108cb72fb7d53d1a16f55'/>
<id>7984922fb252942534a108cb72fb7d53d1a16f55</id>
<content type='text'>
Signed-off-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
Reviewed-by: Bin Meng &lt;bin.meng@windriver.com&gt;
</content>
<content type='xhtml'>
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<pre>
Signed-off-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
Reviewed-by: Bin Meng &lt;bin.meng@windriver.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>riscv: Clean up IPI initialization code</title>
<updated>2020-07-01T07:01:22+00:00</updated>
<author>
<name>Sean Anderson</name>
<email>seanga2@gmail.com</email>
</author>
<published>2020-06-24T10:41:18+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=40686c394e533fec765fe237936e353c84e73fff'/>
<id>40686c394e533fec765fe237936e353c84e73fff</id>
<content type='text'>
The previous IPI code initialized the device whenever the first call was
made to a riscv_*_ipi function. This made it difficult to determine when
the IPI device was initialized. This patch introduces a new function
riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is
called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions
should be called.

Signed-off-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The previous IPI code initialized the device whenever the first call was
made to a riscv_*_ipi function. This made it difficult to determine when
the IPI device was initialized. This patch introduces a new function
riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is
called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions
should be called.

Signed-off-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>common: Drop image.h from common header</title>
<updated>2020-05-18T21:33:33+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-05-10T17:40:01+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4d72caa5b96b71e49b63f98bd8548b194380b544'/>
<id>4d72caa5b96b71e49b63f98bd8548b194380b544</id>
<content type='text'>
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>riscv: Introduce SPL_SMP Kconfig option for U-Boot SPL</title>
<updated>2020-04-23T02:14:06+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2020-04-16T15:09:30+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=191636e4489885d197e61ad34b48e8c76990735e'/>
<id>191636e4489885d197e61ad34b48e8c76990735e</id>
<content type='text'>
With SBI v0.2 HSM extension, only a single hart need to boot and
enter operating system. The booting hart can bring up secondary
harts one by one afterwards.

For U-Boot running in SPL, SMP can be turned on, while in U-Boot
proper, SMP can be optionally turned off if using SBI v0.2 HSM.

Introduce a new SPL_SMP Kconfig option to support this.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
With SBI v0.2 HSM extension, only a single hart need to boot and
enter operating system. The booting hart can bring up secondary
harts one by one afterwards.

For U-Boot running in SPL, SMP can be turned on, while in U-Boot
proper, SMP can be optionally turned off if using SBI v0.2 HSM.

Introduce a new SPL_SMP Kconfig option to support this.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>common: Move hang() to the same header as panic()</title>
<updated>2020-01-17T22:53:40+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-12-28T17:45:07+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=db41d65a97f335167e1fbc0400a83333b5157703'/>
<id>db41d65a97f335167e1fbc0400a83333b5157703</id>
<content type='text'>
At present panic() is in the vsprintf.h header file. That does not seem
like an obvious choice for hang(), even though it relates to panic(). So
let's put hang() in its own header.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
[trini: Migrate a few more files]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
At present panic() is in the vsprintf.h header file. That does not seem
like an obvious choice for hang(), even though it relates to panic(). So
let's put hang() in its own header.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
[trini: Migrate a few more files]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>spl: opensbi: wait for ack from secondary harts before entering OpenSBI</title>
<updated>2019-12-10T00:23:10+00:00</updated>
<author>
<name>Lukas Auer</name>
<email>lukas.auer@aisec.fraunhofer.de</email>
</author>
<published>2019-12-08T22:28:52+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0e1233ce9069a87a84a4385de456665d2bc9229d'/>
<id>0e1233ce9069a87a84a4385de456665d2bc9229d</id>
<content type='text'>
At the start, OpenSBI relocates itself to its link address. If the link
address ranges of U-Boot SPL and OpenSBI overlap, the relocation can
lead to code corruption if a hart is still running U-Boot SPL during
relocation. To avoid this problem, the main hart is specified as the
preferred boot hart to perform the relocation. This fixes the code
corruption problems based on the assumption that since the main hart
schedules the secondary harts to enter OpenSBI, it will be the last to
enter OpenSBI. However it was reported that this assumption is not
always correct.

To make sure the assumption always holds true, wait for all secondary
harts to acknowledge the call-function request before entering OpenSBI
on the main hart.

Reported-by: Rick Chen &lt;rick@andestech.com&gt;
Signed-off-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
Tested-by: Rick Chen &lt;rick@andestech.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
At the start, OpenSBI relocates itself to its link address. If the link
address ranges of U-Boot SPL and OpenSBI overlap, the relocation can
lead to code corruption if a hart is still running U-Boot SPL during
relocation. To avoid this problem, the main hart is specified as the
preferred boot hart to perform the relocation. This fixes the code
corruption problems based on the assumption that since the main hart
schedules the secondary harts to enter OpenSBI, it will be the last to
enter OpenSBI. However it was reported that this assumption is not
always correct.

To make sure the assumption always holds true, wait for all secondary
harts to acknowledge the call-function request before entering OpenSBI
on the main hart.

Reported-by: Rick Chen &lt;rick@andestech.com&gt;
Signed-off-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
Tested-by: Rick Chen &lt;rick@andestech.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>riscv: add option to wait for ack from secondary harts in smp functions</title>
<updated>2019-12-10T00:23:10+00:00</updated>
<author>
<name>Lukas Auer</name>
<email>lukas.auer@aisec.fraunhofer.de</email>
</author>
<published>2019-12-08T22:28:51+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=90ae28143700bae4edd23930a7772899ad259058'/>
<id>90ae28143700bae4edd23930a7772899ad259058</id>
<content type='text'>
Add a wait option to smp_call_function() to wait for the secondary harts
to acknowledge the call-function request. The request is considered to
be acknowledged once each secondary hart has cleared the corresponding
IPI.

As part of the call-function request, the secondary harts invalidate the
instruction cache after clearing the IPI. This adds a delay between
acknowledgment (clear IPI) and fulfillment (call function) of the
request. We want to use the acknowledgment to be able to judge when the
request has been completed. Remove the delay by clearing the IPI after
cache invalidation and just before calling the function from the
request.

Signed-off-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
Tested-by: Rick Chen &lt;rick@andestech.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add a wait option to smp_call_function() to wait for the secondary harts
to acknowledge the call-function request. The request is considered to
be acknowledged once each secondary hart has cleared the corresponding
IPI.

As part of the call-function request, the secondary harts invalidate the
instruction cache after clearing the IPI. This adds a delay between
acknowledgment (clear IPI) and fulfillment (call function) of the
request. We want to use the acknowledgment to be able to judge when the
request has been completed. Remove the delay by clearing the IPI after
cache invalidation and just before calling the function from the
request.

Signed-off-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
Tested-by: Rick Chen &lt;rick@andestech.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>spl: opensbi: specify main hart as preferred boot hart</title>
<updated>2019-12-10T00:23:10+00:00</updated>
<author>
<name>Lukas Auer</name>
<email>lukas.auer@aisec.fraunhofer.de</email>
</author>
<published>2019-12-08T22:28:49+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b86f6d1e649f237849297b5ec6b5566b7a92b2b4'/>
<id>b86f6d1e649f237849297b5ec6b5566b7a92b2b4</id>
<content type='text'>
OpenSBI uses a relocation lottery to determine the hart to relocate
OpenSBI to its link address. In the U-Boot SPL boot flow, the main hart
schedules the secondary harts to enter OpenSBI before doing so itself.
One of the secondary harts will therefore always be the winner of the
relocation lottery. This is problematic if the link address ranges of
OpenSBI and U-Boot SPL overlap. OpenSBI will be relocated and therefore
overwrite U-Boot SPL while some harts may still run it, leading to code
corruption.

Avoid this problem by specifying the main hart as the preferred boot
hart to perform the OpenSBI relocation. The main hart will be the last
hart to enter OpenSBI, relocation can therefore occur safely.

The boot hart field was added to version 2 of the OpenSBI FW_DYNAMIC
info structure. The header file include/opensbi.h is synchronized with
include/sbi/fw_dynamic.h from the OpenSBI project to update the info
structure. The header file is recent as of commit
7a13beb21326 ("firmware: Add preferred boot HART field in struct
fw_dynamic_info").

Reported-by: Rick Chen &lt;rick@andestech.com&gt;
Suggested-by: Anup Patel &lt;Anup.Patel@wdc.com&gt;
Signed-off-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
Tested-by: Rick Chen &lt;rick@andestech.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
OpenSBI uses a relocation lottery to determine the hart to relocate
OpenSBI to its link address. In the U-Boot SPL boot flow, the main hart
schedules the secondary harts to enter OpenSBI before doing so itself.
One of the secondary harts will therefore always be the winner of the
relocation lottery. This is problematic if the link address ranges of
OpenSBI and U-Boot SPL overlap. OpenSBI will be relocated and therefore
overwrite U-Boot SPL while some harts may still run it, leading to code
corruption.

Avoid this problem by specifying the main hart as the preferred boot
hart to perform the OpenSBI relocation. The main hart will be the last
hart to enter OpenSBI, relocation can therefore occur safely.

The boot hart field was added to version 2 of the OpenSBI FW_DYNAMIC
info structure. The header file include/opensbi.h is synchronized with
include/sbi/fw_dynamic.h from the OpenSBI project to update the info
structure. The header file is recent as of commit
7a13beb21326 ("firmware: Add preferred boot HART field in struct
fw_dynamic_info").

Reported-by: Rick Chen &lt;rick@andestech.com&gt;
Suggested-by: Anup Patel &lt;Anup.Patel@wdc.com&gt;
Signed-off-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
Tested-by: Rick Chen &lt;rick@andestech.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</pre>
</div>
</content>
</entry>
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