Find out size directly from header structure. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The patch: "spl: Weed out CONFIG_SYS_TEXT_BASE usage" (sha1: 04ce5427bd3914cab8be78513275a20ab878520a) introduced bug where assigning to u_boot_pos variable wasn't done which end up in situation where SPL wasn't able to find out image on the selected address. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Rockchip-focused changes for v2018.11-rc2: - fixes to rkimage for SPL boot via USB - fixes to make_fit_atf.py, incl. entry-point calculation and python3 compatibility - OP-TEE support for ARMv7-based SoCs - fixes to RGMII/GMII selection on the RK3328 Signed-off-by: Tom Rini <trini@konsulko.com>
OP-TEE is an open source trusted OS, in armv7, its loading and
running are like this:
loading:
- SPL load both OP-TEE and U-Boot
running:
- SPL run into OP-TEE in secure mode;
- OP-TEE run into U-Boot in non-secure mode;
To make code simple, it would be fine to use IH_OS_TEE for the
os tyle in TPL(just like IH_OS_LINUX is using both in SPL and U-Boot).
Here is the diagram for SPL loading OP-TEE,
IH_OS_TEE:(make u-boot.itb for SPL)
Non-Secure Secure
BootROM
|
v
SPL
|
v
--------- OP-TEE
|
v
U-Boot
|
V
Linux
For other two king of OP-TEE loading/booting, see commit message:
45b55712d4 image: Add IH_OS_TEE for TEE chain-load boot
More detail:
https://github.com/OP-TEE/optee_os
and search for 'boot arguments' for detail entry parameter in:
core/arch/arm/kernel/generic_entry_a32.S
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Cc: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This is the PR for SPI-NAND changes along with few spi changes. [trini: Re-sync changes for ls1012afrwy_qspi*_defconfig] Signed-off-by: Tom Rini <trini@konsulko.com>
If we fail to find the MMC boot device, report the number of the one we were looking for in the error to aid diagnosis. Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Xilinx changes for v2018.11 - Handle BOARD_LATE_INIT via Kconfig SPL: - Enable GZIP for all partitions types(not only for kernel) ZynqMP: - Rearrange pmufw version handling - Support newer PMUFW with improved fpga load sequence Zynq: - Cleanup config file - Simplify zybo config by enabling option via Kconfig net: - Fix gems max-speed property reading - Enable support for fixed-link phys
There is no reason to limit gzip usage only for OS_BOOT and kernel image type. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Tested-by: York Sun <york.sun@nxp.com>
The SPL loaders assume that the CONFIG_SYS_TEXT_BASE memory location is available and can be corrupted by loading ie. uImage or fitImage headers there. Sometimes it could be beneficial to load the headers elsewhere, ie. if CONFIG_SYS_TEXT_BASE is not yet writable while we still want to parse the image headers in some local onchip memory to ie. extract firmware from that image. Add the possibility to override the location where the headers get loaded by introducing new function, spl_get_load_buffer() which takes two arguments -- offset from the CONFIG_SYS_TEXT_BASE and size of the data that are to be loaded there -- and returns a valid buffer address or hangs the system. The default behavior is the same as before, add the offset to CONFIG_SYS_TEXT_BASE and return that address. User can override the weak spl_get_load_buffer() function though. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
NAND flavors, like serial and parallel, have a lot in common and would benefit to share code. Let's move raw (parallel) NAND specific code in a raw/ subdirectory, to ease the addition of a core file in nand/ and the introduction of a spi/ subdirectory specific to SPI NANDs. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>