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<title>u-boot.git/common/spl, branch v2023.07-rc4</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
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<updated>2023-05-08T13:26:12Z</updated>
<entry>
<title>common: spl: spl: Remove video driver before u-boot proper</title>
<updated>2023-05-08T13:26:12Z</updated>
<author>
<name>Nikhil M Jain</name>
<email>n-jain1@ti.com</email>
</author>
<published>2023-04-10T08:49:13Z</published>
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<id>urn:sha1:7a17e4c6f1019296a12fc68005916f11de6db928</id>
<content type='text'>
Add method to remove video driver before loading u-boot proper. When
bootstage changes from SPL to u-boot proper, noo method is called to
remove video driver, and at u-boot proper if video driver is not
enabled, the video driver starts displaying garbage on the screen,
because there is no reserved space for video and the frame buffer gets
u-boot proper data written.

Signed-off-by: Nikhil M Jain &lt;n-jain1@ti.com&gt;
</content>
</entry>
<entry>
<title>mmc: Use EXT_CSD_EXTRACT_BOOT_PART() macro for extracting boot part</title>
<updated>2023-04-10T03:18:17Z</updated>
<author>
<name>Pali Rohár</name>
<email>pali@kernel.org</email>
</author>
<published>2023-03-11T10:44:27Z</published>
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<id>urn:sha1:8b8820669646ceb08d6ceed4181b53042639f3ab</id>
<content type='text'>
Mask macro PART_ACCESS_MASK filter out access bits of emmc register and
macro EXT_CSD_EXTRACT_BOOT_PART() extracts boot part bits of emmc register.
So use EXT_CSD_EXTRACT_BOOT_PART() when extracting boot partition.

Signed-off-by: Pali Rohár &lt;pali@kernel.org&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>spl: mmc: Allow to disable SYS_MMCSD_FS_BOOT_PARTITION</title>
<updated>2023-03-01T05:39:17Z</updated>
<author>
<name>Pali Rohár</name>
<email>pali@kernel.org</email>
</author>
<published>2023-01-21T14:13:08Z</published>
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<id>urn:sha1:718d1c749fb2c2c941861afec92b9bd852e824c7</id>
<content type='text'>
On some platforms is SYS_MMCSD_FS_BOOT_PARTITION unsupported. So allow to
completely disable MMC FS Boot support via new option SYS_MMCSD_FS_BOOT.

By default MMC FS Boot support is enabled (like it was before) except for
ARCH_MVEBU where MMC FS Boot supported is unsupported due to Marvell
BootROM limitations.

Signed-off-by: Pali Rohár &lt;pali@kernel.org&gt;
</content>
</entry>
<entry>
<title>spl: Drop unwanted return in spl_fit_upload_fpga()</title>
<updated>2023-02-06T18:04:53Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2023-01-24T10:55:10Z</published>
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<id>urn:sha1:69a3e0779aab4ca4a2f6280fcbfd85bab5ae4256</id>
<content type='text'>
This was added by mistake and renders the function useless. Fix it.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Fixes: 33c60a38bb9 ("trace: Use notrace for short")
Reported-by: Stefan Herbrechtsmeier &lt;stefan.herbrechtsmeier-oss@weidmueller.com&gt;
Reviewed-by: Oleksandr Suvorov &lt;oleksandr.suvorov@foundries.io&gt;
</content>
</entry>
<entry>
<title>spl: sata: Rework the loading case it not use IS_ENABLED(...)</title>
<updated>2023-01-20T17:27:06Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-01-10T16:19:35Z</published>
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<id>urn:sha1:6e73ab32d826d4baca78872dbbaabcf511728bed</id>
<content type='text'>
In this case, using IS_ENABLED(...) to attempt to load the image results
in harder to read and less useful code, along with having to define a
CONFIG value that would be unused. To maintain the current albeit
slightly odd behavior, maintain that if we have both SPL_FS_FAT and
SPL_SATA_RAW_U_BOOT_USE_SECTOR enabled, we use SPL_FS_FAT for the load.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>global: Remove unused CONFIG defines</title>
<updated>2023-01-20T17:27:06Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-01-10T16:19:28Z</published>
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<id>urn:sha1:a3fda0d30afa5e931520006351752cfb9c0103dd</id>
<content type='text'>
Remove some CONFIG symbols and related comments, etc, that are unused
within the code itself at this point.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'dm-pull-18jan23' of https://source.denx.de/u-boot/custodians/u-boot-dm</title>
<updated>2023-01-19T14:46:57Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-01-19T14:46:57Z</published>
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<id>urn:sha1:53c47c59e638cc118c272235db516bb541dad0ac</id>
<content type='text'>
convert rockchip to use binman
patman fix for checkpatch
binman optional entries, improved support for ELF symbols
trace improvements
minor fdt refactoring
</content>
</entry>
<entry>
<title>trace: Use notrace for short</title>
<updated>2023-01-18T18:49:12Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2022-12-21T23:08:15Z</published>
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<id>urn:sha1:33c60a38bb95c9954704857fe5edb29b749b9b18</id>
<content type='text'>
The attribute syntax is quite verbose. Use the macro provided for this
purpose.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>configs: Increase malloc size after relocation</title>
<updated>2023-01-18T18:11:13Z</updated>
<author>
<name>Neha Malcom Francis</name>
<email>n-francis@ti.com</email>
</author>
<published>2023-01-11T12:41:23Z</published>
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<id>urn:sha1:e875cabd7420200529b1dab43602af35afc83430</id>
<content type='text'>
Current default size of 0x100000 is not capable of getting the FIT
buffer during boot when transitioning to using binman generated boot
images for certain K3 devices, so increase it to 0x400000. Since A72 SPL
is coming after relocation to DDR this should not be an issue for any K3
device, so make it default for all.

Signed-off-by: Neha Malcom Francis &lt;n-francis@ti.com&gt;
Acked-by: Andrew Davis &lt;afd@ti.com&gt;
</content>
</entry>
<entry>
<title>arm: rockchip: Add RV1126 arch core support</title>
<updated>2023-01-16T10:01:11Z</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@edgeble.ai</email>
</author>
<published>2022-12-14T17:51:05Z</published>
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<id>urn:sha1:ffb191e458cfbd6584b62b10757f2e68072862cc</id>
<content type='text'>
Rockchip RV1126 is a high-performance vision processor SoC
for IPC/CVR, especially for AI related application.

Add arch core support for it.

Signed-off-by: Jagan Teki &lt;jagan@edgeble.ai&gt;
Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Change-Id: I22fde40ec375e3c6aba39808abf252edc45d4b04
</content>
</entry>
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