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<title>u-boot.git/common/spl, branch v2024.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>sunxi: h616: (really) lower SPL stack address to avoid BROM data</title>
<updated>2023-12-06T23:08:37+00:00</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2022-07-13T15:27:57+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0d8ac5644eaf774c52669921ac4152874c6fc4ca'/>
<id>0d8ac5644eaf774c52669921ac4152874c6fc4ca</id>
<content type='text'>
When using the USB OTG FEL mode on the Allwinner H616, the BootROM
stores some data at the end of SRAM C. This is also the location where
we place the initial SPL stack, so it will overwrite this data.
We still need the BROM code after running the SPL, so should leave that
area alone.
Interestingly this does not seem to have an adverse effect, I guess on
the "way out" (when we return to FEL after the SPL has run), this data
is not needed by the BROM, for just the trailing end of the USB operation.
However this is still wrong, and we should not clobber BROM data.

Lower the SPL stack address to be situated right below the swap buffers
we use in sunxi-fel: that should be out of the way of everyone else.

This obsoletes a previous commit (eb53e7743c8f) with the same name:
that one was changing the address in an *unused* macro in sunxi_common.h,
so the previous patch didn't have any effect at all.

Fixes: eb53e7743c8f ("sunxi: h616: lower SPL stack address to avoid BROM data")
Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
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<pre>
When using the USB OTG FEL mode on the Allwinner H616, the BootROM
stores some data at the end of SRAM C. This is also the location where
we place the initial SPL stack, so it will overwrite this data.
We still need the BROM code after running the SPL, so should leave that
area alone.
Interestingly this does not seem to have an adverse effect, I guess on
the "way out" (when we return to FEL after the SPL has run), this data
is not needed by the BROM, for just the trailing end of the USB operation.
However this is still wrong, and we should not clobber BROM data.

Lower the SPL stack address to be situated right below the swap buffers
we use in sunxi-fel: that should be out of the way of everyone else.

This obsoletes a previous commit (eb53e7743c8f) with the same name:
that one was changing the address in an *unused* macro in sunxi_common.h,
so the previous patch didn't have any effect at all.

Fixes: eb53e7743c8f ("sunxi: h616: lower SPL stack address to avoid BROM data")
Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>tree-wide: Replace http:// link with https:// link for ti.com</title>
<updated>2023-11-10T16:01:50+00:00</updated>
<author>
<name>Nishanth Menon</name>
<email>nm@ti.com</email>
</author>
<published>2023-11-01T20:56:03+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a94a4071d449e12c9fb5ac37d6362d22efcb27da'/>
<id>a94a4071d449e12c9fb5ac37d6362d22efcb27da</id>
<content type='text'>
Replace instances of http://www.ti.com with https://www.ti.com

Signed-off-by: Nishanth Menon &lt;nm@ti.com&gt;
</content>
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<pre>
Replace instances of http://www.ti.com with https://www.ti.com

Signed-off-by: Nishanth Menon &lt;nm@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge tag 'u-boot-imx-20231024' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx</title>
<updated>2023-10-24T13:39:02+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-10-24T13:39:02+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1b2a3d08c0440db4ee37d748b491673f1db0d384'/>
<id>1b2a3d08c0440db4ee37d748b491673f1db0d384</id>
<content type='text'>
u-boot-imx-20231024
-------------------

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/18211

- Fixes for MC2432 Eeprom
- i.MX93 ADC
- Secondary boot mode on i.MX8M
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<pre>
u-boot-imx-20231024
-------------------

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/18211

- Fixes for MC2432 Eeprom
- i.MX93 ADC
- Secondary boot mode on i.MX8M
</pre>
</div>
</content>
</entry>
<entry>
<title>sunxi: add Allwinner R528/T113 SoC support</title>
<updated>2023-10-22T22:41:52+00:00</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2022-09-06T14:59:57+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=95168d77d391b1464af9f99ca44a2e46f309c32e'/>
<id>95168d77d391b1464af9f99ca44a2e46f309c32e</id>
<content type='text'>
This adds the remaining code bits to teach U-Boot about Allwinner's
newest SoC generation. This was introduced with the RISC-V based
Allwinner D1 SoC, which actually shares a die with the ARM cores versions
called R528 (BGA, without DRAM) and T113s (QFP, with embedded DRAM).

This adds the new Kconfig stanza, using the two newly introduced symbols
for the new SoC generation and pincontroller. It also adds the new symbols
to the relavent code places, to set all the hardcoded bits directly.

We need one DT override:
The ARM core version of the DT specifies the CPUX watchdog as
"reserved", which means it won't be recognised by U-Boot. Override this
in our generic sunxi-u-boot.dtsi, to let U-Boot pick up this watchdog,
so that the generic reset driver will work.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
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<pre>
This adds the remaining code bits to teach U-Boot about Allwinner's
newest SoC generation. This was introduced with the RISC-V based
Allwinner D1 SoC, which actually shares a die with the ARM cores versions
called R528 (BGA, without DRAM) and T113s (QFP, with embedded DRAM).

This adds the new Kconfig stanza, using the two newly introduced symbols
for the new SoC generation and pincontroller. It also adds the new symbols
to the relavent code places, to set all the hardcoded bits directly.

We need one DT override:
The ARM core version of the DT specifies the CPUX watchdog as
"reserved", which means it won't be recognised by U-Boot. Override this
in our generic sunxi-u-boot.dtsi, to let U-Boot pick up this watchdog,
so that the generic reset driver will work.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sunxi: introduce NCAT2 generation model</title>
<updated>2023-10-22T22:41:46+00:00</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2022-10-05T16:54:19+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4a9e89a3e390bbff31aec25f9ec6d32e29e355f5'/>
<id>4a9e89a3e390bbff31aec25f9ec6d32e29e355f5</id>
<content type='text'>
Allwinner seems to typically stick to a common MMIO memory map for
several SoCs, but from time to time does some breaking changes, which
also introduce new generations of some peripherals. The last time this
happened with the H6, which apart from re-organising the base addresses
also changed the clock controller significantly. We added a
CONFIG_SUN50I_GEN_H6 symbol back then to mark SoCs sharing those traits.

Now the Allwinner D1 changes the memory map again, and also extends the
pincontroller, among other peripherals.
To mark this generation of SoCs, add a CONFIG_SUNXI_GEN_NCAT2 symbol,
this name is reportedly used in the Allwinner BSP code, and prevents us
from inventing our own name.

Add this new symbol to some guards that were already checking for the H6
generation, since many features are shared between the two (like the
renovated clock controller).

This paves the way to introduce a first user of this generation.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Tested-by: Samuel Holland &lt;samuel@sholland.org&gt;
</content>
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<pre>
Allwinner seems to typically stick to a common MMIO memory map for
several SoCs, but from time to time does some breaking changes, which
also introduce new generations of some peripherals. The last time this
happened with the H6, which apart from re-organising the base addresses
also changed the clock controller significantly. We added a
CONFIG_SUN50I_GEN_H6 symbol back then to mark SoCs sharing those traits.

Now the Allwinner D1 changes the memory map again, and also extends the
pincontroller, among other peripherals.
To mark this generation of SoCs, add a CONFIG_SUNXI_GEN_NCAT2 symbol,
this name is reportedly used in the Allwinner BSP code, and prevents us
from inventing our own name.

Add this new symbol to some guards that were already checking for the H6
generation, since many features are shared between the two (like the
renovated clock controller).

This paves the way to introduce a first user of this generation.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Tested-by: Samuel Holland &lt;samuel@sholland.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>spl: riscv: add os type for next booting stage</title>
<updated>2023-10-19T09:29:33+00:00</updated>
<author>
<name>Randolph</name>
<email>randolph@andestech.com</email>
</author>
<published>2023-10-12T06:35:07+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=58fa2a5aa164fd8b516bd66649bbb595ebf1540c'/>
<id>58fa2a5aa164fd8b516bd66649bbb595ebf1540c</id>
<content type='text'>
If SPL_LOAD_FIT_OPENSBI_OS_BOOT is enabled, the function
spl_invoke_opensbi should change the target OS type to IH_OS_LINUX.
OpenSBI will load the Linux image as the next boot stage.
The os_takes_devicetree function returns a value of true or false
depending on whether or not SPL_LOAD_FIT_OPENSBI_OS_BOOT is enabled.

Signed-off-by: Randolph &lt;randolph@andestech.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
If SPL_LOAD_FIT_OPENSBI_OS_BOOT is enabled, the function
spl_invoke_opensbi should change the target OS type to IH_OS_LINUX.
OpenSBI will load the Linux image as the next boot stage.
The os_takes_devicetree function returns a value of true or false
depending on whether or not SPL_LOAD_FIT_OPENSBI_OS_BOOT is enabled.

Signed-off-by: Randolph &lt;randolph@andestech.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>spl: riscv: opensbi: change the default os_type as varible</title>
<updated>2023-10-19T09:29:33+00:00</updated>
<author>
<name>Randolph</name>
<email>randolph@andestech.com</email>
</author>
<published>2023-10-12T06:35:03+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5367b9e798279bd28d920212e842f637eec359bc'/>
<id>5367b9e798279bd28d920212e842f637eec359bc</id>
<content type='text'>
In order to introduce the Opensbi OS boot mode, the next stage boot
image of OpenSBI should be configurable.

Signed-off-by: Randolph &lt;randolph@andestech.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
In order to introduce the Opensbi OS boot mode, the next stage boot
image of OpenSBI should be configurable.

Signed-off-by: Randolph &lt;randolph@andestech.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>spl: Use map_sysmem where appropriate</title>
<updated>2023-10-18T00:50:52+00:00</updated>
<author>
<name>Sean Anderson</name>
<email>seanga2@gmail.com</email>
</author>
<published>2023-10-14T20:47:55+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b02c4e941c7fed520f05cc956b9263bc934a9828'/>
<id>b02c4e941c7fed520f05cc956b9263bc934a9828</id>
<content type='text'>
All "physical" addresses in SPL must be converted to virtual addresses
before access in order for sandbox to work. Add some calls to map_sysmem in
appropriate places. We do not generally call unmap_sysmem, since we need
the image memory to still be mapped when we jump to the image. This doesn't
matter at the moment since unmap_sysmem is a no-op.

Signed-off-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
All "physical" addresses in SPL must be converted to virtual addresses
before access in order for sandbox to work. Add some calls to map_sysmem in
appropriate places. We do not generally call unmap_sysmem, since we need
the image memory to still be mapped when we jump to the image. This doesn't
matter at the moment since unmap_sysmem is a no-op.

Signed-off-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>spl: Add callbacks to invalidate cached devices</title>
<updated>2023-10-18T00:50:52+00:00</updated>
<author>
<name>Sean Anderson</name>
<email>seanga2@gmail.com</email>
</author>
<published>2023-10-14T20:47:54+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=93caa3efe25bb9d3e6265aa467dc5b6a2201819b'/>
<id>93caa3efe25bb9d3e6265aa467dc5b6a2201819b</id>
<content type='text'>
Several SPL functions try to avoid performing initialization twice by
caching devices. This is fine for regular boot, but does not work with
UNIT_TEST, since all devices are torn down after each test. Add some
functions to invalidate the caches which can be called before testing these
load methods.

Signed-off-by: Sean Anderson &lt;seanga2@gmail.com&gt;
</content>
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<pre>
Several SPL functions try to avoid performing initialization twice by
caching devices. This is fine for regular boot, but does not work with
UNIT_TEST, since all devices are torn down after each test. Add some
functions to invalidate the caches which can be called before testing these
load methods.

Signed-off-by: Sean Anderson &lt;seanga2@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fs: ext4: Fix building ext4 in SPL if write is enabled</title>
<updated>2023-10-18T00:50:52+00:00</updated>
<author>
<name>Sean Anderson</name>
<email>seanga2@gmail.com</email>
</author>
<published>2023-10-14T20:47:49+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=44071cd5a8b1719397fe818d1c6ebc67a5db1953'/>
<id>44071cd5a8b1719397fe818d1c6ebc67a5db1953</id>
<content type='text'>
If EXT4_WRITE is enabled, write capabilities will be compiled into SPL, but
not CRC16. Add an option to enable CRC16 to avoid linker errors.

Signed-off-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
If EXT4_WRITE is enabled, write capabilities will be compiled into SPL, but
not CRC16. Add an option to enable CRC16 to avoid linker errors.

Signed-off-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
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