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<title>u-boot.git/common/spl, branch v2024.07-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>Merge branch 'next'</title>
<updated>2024-04-02T11:03:25+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-04-02T11:03:25+00:00</published>
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<id>d312d9831f25a8e70d64df46fb2fe9aab2e8c939</id>
<content type='text'>
Merge in all changes from the next branch now that the release is out.
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<pre>
Merge in all changes from the next branch now that the release is out.
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</entry>
<entry>
<title>spl: riscv: opensbi: fix check of PAYLOAD_ARGS_ADDR</title>
<updated>2024-03-26T09:31:24+00:00</updated>
<author>
<name>Randolph</name>
<email>randolph@andestech.com</email>
</author>
<published>2024-03-22T11:36:37+00:00</published>
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<id>0cfe1bc6ed9b322d2b03ded3175ac5de3ed2b784</id>
<content type='text'>
When Falcon Mode is enabled on RISC-V, use CONFIG_VAL
to check PAYLOAD_ARGS_ADDR, not CONFIG_IS_ENABLED.

Fixes: 10c4ab898c25 ("spl: riscv: falcon: move fdt blob to specified address")
Signed-off-by: Randolph &lt;randolph@andestech.com&gt;
Tested-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
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<pre>
When Falcon Mode is enabled on RISC-V, use CONFIG_VAL
to check PAYLOAD_ARGS_ADDR, not CONFIG_IS_ENABLED.

Fixes: 10c4ab898c25 ("spl: riscv: falcon: move fdt blob to specified address")
Signed-off-by: Randolph &lt;randolph@andestech.com&gt;
Tested-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>spl: Improve error message for SPL memory allocation</title>
<updated>2024-03-20T21:12:38+00:00</updated>
<author>
<name>Leo Yu-Chi Liang</name>
<email>ycliang@andestech.com</email>
</author>
<published>2024-03-13T06:53:15+00:00</published>
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<id>aeda4ccf3c60ab1ed43cc994d01fb93e39993ca1</id>
<content type='text'>
There could be two memory allocation scheme in SPL phase.
Explicitly print the corresponding error message.

Signed-off-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
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<pre>
There could be two memory allocation scheme in SPL phase.
Explicitly print the corresponding error message.

Signed-off-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>log: fixup log_head after relocating global data</title>
<updated>2024-03-02T17:26:56+00:00</updated>
<author>
<name>Thomas Weißschuh</name>
<email>thomas.weissschuh@linutronix.de</email>
</author>
<published>2024-02-13T17:13:28+00:00</published>
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<id>39162d9348584ad6d86cb2a3a540ca38f8be7ff8</id>
<content type='text'>
When `gd` is relocated during `spl_relocate_stack_gd()` the
doubly-linked circular list in the `log_head` member is broken.

The last element of the list should point back to the initial
`list_head`, but as the initial `list_head` is moved the pointer becomes
stale. As a result the loop in `log_dispatch` would never finish.

Signed-off-by: Thomas Weißschuh &lt;thomas.weissschuh@linutronix.de&gt;
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<pre>
When `gd` is relocated during `spl_relocate_stack_gd()` the
doubly-linked circular list in the `log_head` member is broken.

The last element of the list should point back to the initial
`list_head`, but as the initial `list_head` is moved the pointer becomes
stale. As a result the loop in `log_dispatch` would never finish.

Signed-off-by: Thomas Weißschuh &lt;thomas.weissschuh@linutronix.de&gt;
</pre>
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</content>
</entry>
<entry>
<title>spl: Make SPL_STACK available for ROCKCHIP_RK3036 without spl framework</title>
<updated>2024-02-04T10:01:03+00:00</updated>
<author>
<name>Kever Yang</name>
<email>kever.yang@rock-chips.com</email>
</author>
<published>2024-01-24T07:42:04+00:00</published>
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<id>ce7ae9d2dbe1190153157bddfdefb121f09e1e3e</id>
<content type='text'>
rk3036 soc has limit internal sram, and not able to support spl
framework.

Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
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<pre>
rk3036 soc has limit internal sram, and not able to support spl
framework.

Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>spl: riscv: falcon: move fdt blob to specified address</title>
<updated>2024-01-31T08:51:03+00:00</updated>
<author>
<name>Randolph</name>
<email>randolph@andestech.com</email>
</author>
<published>2023-12-29T08:32:22+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=10c4ab898c251a9f8d79b525880a1751b4815350'/>
<id>10c4ab898c251a9f8d79b525880a1751b4815350</id>
<content type='text'>
In Falcon Boot mode, the fdt blob should be move to the RAM from
kernel BSS section. To avoid being cleared by BSS initialisation.
SPL_PAYLOAD_ARGS_ADDR is the address where SPL copies.

Signed-off-by: Randolph &lt;randolph@andestech.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
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<pre>
In Falcon Boot mode, the fdt blob should be move to the RAM from
kernel BSS section. To avoid being cleared by BSS initialisation.
SPL_PAYLOAD_ARGS_ADDR is the address where SPL copies.

Signed-off-by: Randolph &lt;randolph@andestech.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge patch series "Move framebuffer reservation for SPL to RAM end"</title>
<updated>2024-01-29T19:49:25+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-01-29T19:49:25+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=073f4f10b9941c7b3cec7db41c82ac00b811eaba'/>
<id>073f4f10b9941c7b3cec7db41c82ac00b811eaba</id>
<content type='text'>
Devarsh Thakkar &lt;devarsht@ti.com&gt; says:

Move video memory reservation for SPL at end of RAM so that it does
not interefere with reservations for next stage so that the next stage
need not have holes in between for passed regions and instead it can
maintain continuity in reservations.

Also catch the bloblist before starting reservations to avoid the same
problem.

While at it, also fill missing fields in video handoff struct before
passing it to next stage.

This is as per discussions at :
For moving SPL framebuffer reservation at end of RAM:

https://lore.kernel.org/all/CAPnjgZ3xSoe_G3yrqwuAvoiVjUfZ+YQgkOR0ZTVXGT9VK8TwJg@mail.gmail.com/

For filling missing video handoff fields :
https://lore.kernel.org/all/CAPnjgZ1Hs0rNf0JDirp6YPsOQ5=QqQSP9g9qRwLoOASUV8a4cw@mail.gmail.com/
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<pre>
Devarsh Thakkar &lt;devarsht@ti.com&gt; says:

Move video memory reservation for SPL at end of RAM so that it does
not interefere with reservations for next stage so that the next stage
need not have holes in between for passed regions and instead it can
maintain continuity in reservations.

Also catch the bloblist before starting reservations to avoid the same
problem.

While at it, also fill missing fields in video handoff struct before
passing it to next stage.

This is as per discussions at :
For moving SPL framebuffer reservation at end of RAM:

https://lore.kernel.org/all/CAPnjgZ3xSoe_G3yrqwuAvoiVjUfZ+YQgkOR0ZTVXGT9VK8TwJg@mail.gmail.com/

For filling missing video handoff fields :
https://lore.kernel.org/all/CAPnjgZ1Hs0rNf0JDirp6YPsOQ5=QqQSP9g9qRwLoOASUV8a4cw@mail.gmail.com/
</pre>
</div>
</content>
</entry>
<entry>
<title>spl: Enforce framebuffer reservation from end of RAM</title>
<updated>2024-01-29T19:49:17+00:00</updated>
<author>
<name>Devarsh Thakkar</name>
<email>devarsht@ti.com</email>
</author>
<published>2023-12-05T15:55:16+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1d3c266758570ea7d329746ae2d5b31fb12b9f61'/>
<id>1d3c266758570ea7d329746ae2d5b31fb12b9f61</id>
<content type='text'>
Add an API which enforces framebuffer reservation from end of RAM.
This is done so that next stage can directly skip this region before
carrying out further reservations.

Signed-off-by: Devarsh Thakkar &lt;devarsht@ti.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
Add an API which enforces framebuffer reservation from end of RAM.
This is done so that next stage can directly skip this region before
carrying out further reservations.

Signed-off-by: Devarsh Thakkar &lt;devarsht@ti.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sunxi: Consider SPL size limitations for FIT loading</title>
<updated>2024-01-29T14:31:00+00:00</updated>
<author>
<name>Samuel Holland</name>
<email>samuel@sholland.org</email>
</author>
<published>2023-10-31T05:17:41+00:00</published>
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<content type='text'>
Now that 32-bit SoCs can load U-Boot proper (and possibly other firmware)
from a FIT, people can use that by enabling CONFIG_SPL_LOAD_FIT.
However SPL_FIT_IMAGE_TINY is required to stay within the 24 or 32 KiB
SPL size limit on early SoCs; for consistency, enable it everywhere.

Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
[Andre: drop unconditional FIT image enablement for all SoCs]
Reviewed-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
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<pre>
Now that 32-bit SoCs can load U-Boot proper (and possibly other firmware)
from a FIT, people can use that by enabling CONFIG_SPL_LOAD_FIT.
However SPL_FIT_IMAGE_TINY is required to stay within the 24 or 32 KiB
SPL size limit on early SoCs; for consistency, enable it everywhere.

Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
[Andre: drop unconditional FIT image enablement for all SoCs]
Reviewed-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sunxi: spl: Disable padding from SPL_PAD_TO</title>
<updated>2024-01-29T14:30:59+00:00</updated>
<author>
<name>Samuel Holland</name>
<email>samuel@sholland.org</email>
</author>
<published>2023-10-31T05:17:38+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d72494a06443061f150742910e9441fe9c9e14f3'/>
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<content type='text'>
Starting with H6, Allwinner removed the artificial 32 KiB SPL size limit
from the boot ROM. Now SPL size is only limited by the available SRAM.
This limit ranges from 152 KiB on H6 to a whopping 2052 KiB on R329. To
take advantage of this additional space, we must increase SPL_MAX_SIZE.
Since we do not want to unnecessarily pad SPL out to these giant sizes,
we must set SPL_PAD_TO to zero. This causes no problems because binman
already takes care of appending the SPL payload at the right offset.

Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
Reviewed-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
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<pre>
Starting with H6, Allwinner removed the artificial 32 KiB SPL size limit
from the boot ROM. Now SPL size is only limited by the available SRAM.
This limit ranges from 152 KiB on H6 to a whopping 2052 KiB on R329. To
take advantage of this additional space, we must increase SPL_MAX_SIZE.
Since we do not want to unnecessarily pad SPL out to these giant sizes,
we must set SPL_PAD_TO to zero. This causes no problems because binman
already takes care of appending the SPL payload at the right offset.

Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
Reviewed-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</pre>
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</content>
</entry>
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