The PCIe0 instance of PCIe on the AM64x SoC uses the 4 GB Address Window
starting from 0x6_0000_0000 to map System Addresses to PCIe Bus Addresses.
Hence, enable CONFIG_SYS_PCI_64BIT.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Fixes: 79f3e77133bd ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream")
This series from Andrew Davis <afd@ti.com> makes a number of the TI K3 CONFIG symbols have consistent values in SPL, as they are things determined by the SoC and not the board design. Link: https://lore.kernel.org/r/20251208190635.2044082-1-afd@ti.com
These are common for all K3 based boards. Add the common values as defaults and remove from each board defconfig Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com>
The DA8xx GPIO driver was not being built as part of the A53 U-Boot image on AM64x and AM65x. This meant only i2c GPIO expanders were accessible to the users from the U-Boot prompt. This patch fixes it by setting CONFIG_DA8XX_GPIO. Signed-off-by: Anshul Dalal <anshuld@ti.com>
Commit 86acdce2ba88 ("common: add config for board_init() call")
introduced CONFIG_BOARD_INIT option. This option can be disabled for the
boards where board_init() function is not needed. Remove empty
board_init() calls for all boards where it's possible, and disable
CONFIG_BOARD_INIT in all related defconfigs.
This cleanup was made semi-automatically using these scripts: [1].
No functional change, but the binary size for the modified boards is
reduced a bit.
[1] https://github.com/joe-skb7/uboot-convert-scripts/tree/master/remove-board-init
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Tested-by: Adam Ford <aford173@gmail.com> #imx8mm_beacon
Tested-by: Bryan Brattlof <bb@ti.com>
Acked-by: Peng Fan <peng.fan@nxp.com> #NXP boards
Hrushikesh Salunke <h-salunke@ti.com> says: This series adds support for the Endpoint mode on Cadence PCIe controller on TI's K3 family of SoCs. The driver is an adaptation of the Linux driver (drivers/pci/controller/cadence/pci-j721e.c) and has been implemented specifically for Endpoint mode of operation on AM64X. A minor set of changes will be sufficient to support other K3 SoCs as well. This patch is tested on AM64X EVM. Following are the log corresponding to this feature. https://gist.github.com/hrushikesh221/e8557cbe7667877c50f7d7e9bb96d060 Link: https://lore.kernel.org/r/20250616164929.631791-1-h-salunke@ti.com
TI's AM64x SoC has a single instance of PCIe Controller namely PCIe0 which is a Cadence PCIe Controller. To support PCI Endpoint functionality with the PCIe0 instance of PCIe, enable the corresponding configs. Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
Use default value of malloc size coming from Kconfig, instead of board specific override. Signed-off-by: Udit Kumar <u-kumar1@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Enable UHS modes for SD by enabling configs for voltage regulator drivers, IO voltage switching, and configs to support UHS modes. The am64x SoC has an internal LDO which does voltage switching, but the MMC_IO_VOLTAGE config is still required to be able to switch voltage for SD. While we are here, am64x HS400 mode has been descoped as per datasheet [0] even though we still initialize to HS200, clean this up by switching to MMC_HS200_SUPPORT config options. [0] https://www.ti.com/lit/gpn/am6442 Signed-off-by: Judith Mendez <jm@ti.com>
Hrushikesh Salunke <h-salunke@ti.com> says: TI's AM64 SoC has a single instance of Cadence PCIe Controller. This series enables support for PCIe in AM64 SoC and to configure it in Root-Complex mode of operation. Link: https://lore.kernel.org/r/20250416120830.138965-1-h-salunke@ti.com