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<title>u-boot.git/configs, branch v2018.01-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/configs?h=v2018.01-rc2</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/configs?h=v2018.01-rc2'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2017-12-19T01:19:09Z</updated>
<entry>
<title>configs: Resync with savedefconfig</title>
<updated>2017-12-19T01:19:09Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2017-12-19T01:19:09Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7af2e3648f3f6d726f6476745c2eec5de709a702'/>
<id>urn:sha1:7af2e3648f3f6d726f6476745c2eec5de709a702</id>
<content type='text'>
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>Merge git://git.denx.de/u-boot-rockchip</title>
<updated>2017-12-18T23:39:18Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2017-12-18T23:39:18Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=eeab579aa8d76b96afbd0862029d4452943bafbe'/>
<id>urn:sha1:eeab579aa8d76b96afbd0862029d4452943bafbe</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Merge git://git.denx.de/u-boot-fsl-qoriq</title>
<updated>2017-12-18T23:39:00Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2017-12-18T23:39:00Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1a3fc354b50b2a86361964b6d695ce26058248f5'/>
<id>urn:sha1:1a3fc354b50b2a86361964b6d695ce26058248f5</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Merge tag 'xilinx-for-v2018.01-rc2-v2' of git://www.denx.de/git/u-boot-microblaze</title>
<updated>2017-12-18T17:23:27Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2017-12-18T17:23:27Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=90d75d2efc376094b50d84de80e9cb8b3bcae032'/>
<id>urn:sha1:90d75d2efc376094b50d84de80e9cb8b3bcae032</id>
<content type='text'>
Xilinx changes for v2018.01-rc2-v2

fpga:
- Enable loading bitstream via fit image for !xilinx platforms

zynq:
- Fix SPL SD boot mode

zynqmp:
- Not not reset in panic
- Do not use simple allocator because of fat changes
- Various dt chagnes
- modeboot variable setup
- Fix fpga loading on automotive devices
- Fix coverity issues

test:
- Fix env test for !hush case - Stephen's patch
</content>
</entry>
<entry>
<title>rockchip: firefly-rk3399: add FIT for rk3399</title>
<updated>2017-12-18T16:18:02Z</updated>
<author>
<name>Kever Yang</name>
<email>kever.yang@rock-chips.com</email>
</author>
<published>2017-12-15T03:15:04Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1a066c22f233fcf59b2e8cddf295b98b6998e037'/>
<id>urn:sha1:1a066c22f233fcf59b2e8cddf295b98b6998e037</id>
<content type='text'>
Enable SPL_FIT_GENERATOR with path for it.
With this patch you can get u-boot.itb for rk3399-firefly with:
&gt; make u-boot.itb

Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Reviewed-by: Mark Kettenis &lt;kettenis@openbsd.org&gt;
Tested-by: Mark Kettenis &lt;kettenis@openbsd.org&gt;
Acked-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</content>
</entry>
<entry>
<title>rockchip: update ROCKCHIP_SPL_RESERVE_IRAM to 0</title>
<updated>2017-12-18T15:56:17Z</updated>
<author>
<name>Kever Yang</name>
<email>kever.yang@rock-chips.com</email>
</author>
<published>2017-12-18T07:13:19Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8a8106f06639314f750c9f8dc2b72df3925f7fbf'/>
<id>urn:sha1:8a8106f06639314f750c9f8dc2b72df3925f7fbf</id>
<content type='text'>
Only rk3399 atf need ROCKCHIP_SPL_RESERVE_IRAM. This commit updates
its default setting to 0 so that other SoCs do not need to define it.

Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Acked-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</content>
</entry>
<entry>
<title>arm64: zynqmp: Dont use 4K sector erase by default for spi-flashes</title>
<updated>2017-12-18T08:32:06Z</updated>
<author>
<name>Siva Durga Prasad Paladugu</name>
<email>siva.durga.paladugu@xilinx.com</email>
</author>
<published>2017-01-31T05:14:06Z</published>
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<id>urn:sha1:3a55cb38c5335901be9550d77f7672ae37f0fa99</id>
<content type='text'>
Dont use 4K sector erase by default, Disabling this
would use 64K sector erase and decreases erase time.
Also disabled by the fact that UBIFS and JFFS2 won't work
with 4K sector erase.

Signed-off-by: Siva Durga Prasad Paladugu &lt;sivadur@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
<entry>
<title>arm64: zynqmp: Enable spi flashes</title>
<updated>2017-12-18T08:32:06Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2017-12-08T14:18:05Z</published>
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<id>urn:sha1:877017eea37c17269596bc820f1cd814e383ee48</id>
<content type='text'>
Enabling all spi flashes because some of these boards can have different
flashes compared to public version.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
<entry>
<title>arm64: zynqmp: Enable fpga bitstream loading</title>
<updated>2017-12-14T19:08:49Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2017-12-08T14:03:26Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=67e556dfb12ca0c88c752826208e5a4c80192905'/>
<id>urn:sha1:67e556dfb12ca0c88c752826208e5a4c80192905</id>
<content type='text'>
Enable fpga loadb and loadbp for zynqmp platforms.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
<entry>
<title>arm64: zynqmp: Enable SPL ram support</title>
<updated>2017-12-14T19:08:49Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2017-12-08T14:01:19Z</published>
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<id>urn:sha1:a92268fd7ccbb60c5911a4d66fe1abe8d96904cb</id>
<content type='text'>
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
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