Unnamed repository; edit this file 'description' to name the repository. http://cgit.235523.xyz/u-boot.git/atom/configs?h=v2020.01-rc2 2019-11-12T01:04:24Z 2019-11-12T01:04:24Z Tom Rini trini@konsulko.com 2019-11-12T01:04:24Z urn:sha1:59e5d1e2a51592d33cd5758d746006db96d99163 Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com> 2019-11-11T19:19:32Z Tom Rini trini@konsulko.com 2019-11-11T19:19:32Z urn:sha1:086e391bc46d3dda5c44053532bb51dc3827ee94 - Add support for rockchip pmic rk805,rk809, rk816, rk817 - Add rk3399 board Leez support - Fix bug in rk3328 ram driver - Adapt SPL to support ATF bl31 with entry at 0x40000 - Fix the u8 type comparision with '-1'. - Fix checkpatch warning for multi blank line and review signature. 2019-11-11T19:19:04Z Tom Rini trini@konsulko.com 2019-11-11T19:19:04Z urn:sha1:0b73ef0c02313e651af4b0a8e206c7c4a198e7f8 - Rename CONFIG_SECURE_BOOT to CONFIG_NXP_ESBC. - Few bug fixes and updates related to SPI, hwconfig, ethernet, fsl-layerscape, pci, icid, PSCI 2019-11-10T12:40:20Z Kever Yang kever.yang@rock-chips.com 2019-10-16T08:50:03Z urn:sha1:f74a089e47e0b485fb70dcadfbf093daf64a740a This patch enable TPL support for firefly-rk3288 board, which works ths same way with other RK3288 board like Tinker, evb. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> 2019-11-10T12:40:20Z Kever Yang kever.yang@rock-chips.com 2019-10-18T07:54:15Z urn:sha1:006ab58d4636124f617174fa2dfe24739874ee91 Use the same SPL_STACK_R_ADDR in Kconfig instead of each board config; default to 0x4000000(64MB) instead of 0x80000(512KB) for this address can support all the SoCs including those may have only 64MB memory, and also reserve enough space for atf, kernel(in falcon mode) loading. After the ATF entry move to 0x40000, the stack from 0x80000 may be override when loading ATF bl31. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> 2019-11-10T12:40:20Z Kever Yang kever.yang@rock-chips.com 2019-10-23T03:10:36Z urn:sha1:4b294886d03e9989d6ff163eef04da4927f75952 We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code, and when we introduce the TPL, the SPL space is in DRAM, we reserve space to avoid SPL text overlap with ATF bl31. Now we decide to move ATF entry point to 0x40000 instead of 0x1000, so that the SPL can have 0x4000 as code size and no need to reserve space or relocate before loading ATF. The mainline ATF has update since: 0aad563c rockchip: Update BL31_BASE to 0x40000 Signed-off-by: Kever Yang <kever.yang@rock-chips.com> 2019-11-10T12:40:20Z Kever Yang kever.yang@rock-chips.com 2019-10-23T02:08:53Z urn:sha1:ae2500f89a8de636a2a23187010fa57f44ac3bd3 We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code, and when we introduce the TPL, the SPL space is in DRAM, we reserve space to avoid SPL text overlap with ATF bl31. Now we decide to move ATF entry point to 0x40000 instead of 0x1000, so that the SPL can have 0x4000 as code size and no need to reserve space or relocate before loading ATF. The mainline ATF has update since: 0aad563c rockchip: Update BL31_BASE to 0x40000 Signed-off-by: Kever Yang <kever.yang@rock-chips.com> 2019-11-10T12:40:20Z Kever Yang kever.yang@rock-chips.com 2019-10-18T07:54:14Z urn:sha1:5ce94c74a6b59922d4280573f2438e4f5f9b29a8 We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code, and when we introduce the TPL, the SPL space is in DRAM, we reserve space to avoid SPL text overlap with ATF bl31. Now we decide to move ATF entry point to 0x40000 instead of 0x1000, so that the SPL can have 0x4000 as code size and no need to reserve space or relocate before loading ATF. The mainline ATF has update since: 0aad563c rockchip: Update BL31_BASE to 0x40000 Signed-off-by: Kever Yang <kever.yang@rock-chips.com> 2019-11-10T12:40:20Z Andy Yan andyshrk@gmail.com 2019-09-22T10:06:56Z urn:sha1:a4bbc662fc7cea596e94ad8623202df7a2c50e27 Specification - Rockchip RK3399 - LPDDR4 - TF sd scard slot - eMMC - M.2 B-Key for 4G LTE - AP6256 for WiFi + BT - Gigabit ethernet - HDMI out - 40 pin header - USB 2.0 x 2 - USB 3.0 x 1 - USB 3.0 Type-C x 1 - TYPE-C Power supply Commit details of rk3399-leez-p710.dts sync from linus tree for Linux 5.4-rc1: "arm64: dts: rockchip: Add dts for Leez RK3399 P710 SBC" (sha1: fc702ed49a8668a17343811ee28214d845bfc5e6) Signed-off-by: Andy Yan <andyshrk@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> 2019-11-08T12:27:45Z Tom Rini trini@konsulko.com 2019-11-08T12:27:45Z urn:sha1:ee1c499851e0fda1a6ab98fb1f1d1f672e64a6f8 - Add Phytium Durian Board - Assorted bugfixes - Allow for make ERR_PTR/PTR_ERR architecture specific