u-boot.git/cpu/74xx_7xx/cache.S, branch master

ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU

2010-04-13T07:13:16+00:00

Signed-off-by: Peter Tyser

rename CFG_ macros to CONFIG_SYS

2008-10-18T19:54:03+00:00

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD

74xx/7xx/86xx: Rename flush_data_cache to flush_dcache to match 85xx version

2008-10-18T19:54:02+00:00

Signed-off-by: Kumar Gala

Clean up usage of icache_disable/dcache_disable

2008-08-18T22:57:28+00:00

There is no point in disabling the icache on 7xx/74xx/86xx parts and not
also flushing the icache.  All callers of invalidate_l1_instruction_cache()
call icache_disable() right after.  Make it so icache_disable() calls
invalidate_l1_instruction_cache() for us.

Also, dcache_disable() already calls dcache_flush() so there is no point
in the explicit calls of dcache_flush().

Signed-off-by: Kumar Gala

7450 and 86xx L2 cache invalidate bug corrections

2008-05-09T18:46:48+00:00

The 7610 and related parts have an L2IP bit in the L2CR that is
monitored to signal when the L2 cache invalidate is complete whereas the
7450 and related parts utilize L2I for this purpose. However, the
current code does not account for this difference. Additionally the 86xx
L2 cache invalidate code used an "andi" instruction where an "andis"
instruction should have been used.

This patch addresses both of these bugs.

Signed-off-by: Travis Wheatley 
Acked-By: Jon Loeliger

* Patch by Jim Sandoz, 07 Nov 2002:

2002-11-11T21:14:20+00:00

  Increase number of network RX buffers (PKTBUFSRX in
  "include/net.h") for EEPRO100 based boards (especially SP8240)
  which showed "Receiver is not ready" errors when U-Boot was
  processing the receive buffers slower than the network controller
  was filling them.

* Get rid of obsolete include/mpc74xx.h

Initial revision

2002-11-03T00:38:21+00:00