u-boot.git/cpu/arm926ejs/versatile/timer.c, branch v2008.10Unnamed repository; edit this file 'description' to name the repository.http://cgit.235523.xyz/u-boot.git/atom/cpu/arm926ejs/versatile/timer.c?h=v2008.102008-08-25T11:00:03ZCorrect ARM Versatile Timer Initialization2008-08-25T11:00:03ZGururaja Hebbar K Rgururajakr@sanyo.co.in2008-08-25T09:11:34Zurn:sha1:e8f1207bbf2df6fb693ee1aa3329b2014c92e5e6
- According to ARM Dual-Timer Module (SP804) TRM (ARM DDI0271),
-- Timer Value Register @ TIMER Base + 4 is Read-only.
-- Prescale Value (Bits 3-2 of TIMER Control register)
can only be one of 00,01,10. 11 is undefined.
-- CFG_HZ for Versatile board is set to
#define CFG_HZ (1000000 / 256)
So Prescale bits is set to indicate
- 8 Stages of Prescale, Clock divided by 256
- The Timer Control Register has one Undefined/Shouldn't Use Bit
So we should do read/modify/write Operation
Signed-off-by: Gururaja Hebbar <gururajakr@sanyo.co.in>
Apply SoC concept to arm926ejs CPUs, i.e. move the SoC specific timer and2006-03-13T11:37:35ZWolfgang Denkwd@pollux.denx.de2006-03-13T11:37:35Zurn:sha1:ff7fefe6797246b2748530f965f2e41de34a982a
cpu_reset code from cpu/$(CPU) into the new cpu/$(CPU)/$(SOC) directories
Patch by Andreas Engel, 13 Mar 2006