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<title>u-boot.git/cpu/arm_cortexa8/cpu.c, branch v2010.03</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>OMAP3 Move cache routine to cache.S</title>
<updated>2009-10-13T11:17:33+00:00</updated>
<author>
<name>Tom Rix</name>
<email>Tom.Rix@windriver.com</email>
</author>
<published>2009-09-10T19:27:57+00:00</published>
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<id>7a2aa8b68120f333ed2edc33475ca195810d6cb1</id>
<content type='text'>
v7_flush_dcache_all, because it depends on omap ROM code is not
generic.  Rename the function to 'invalidate_dcache' and move it
to the omap cpu directory.

Collect the other omap cache routines l2_cache_enable and
l2_cache_disable with invalide_dcache into cache.S.  This
means removing the old cache.c file that contained l2_cache_enable
and l2_cache_disable.

The conversion from cache.c to cache.S was done most through
disassembling the uboot binary.  The only significant change was
to change the comparision for the return of get_cpu_rev from

   cmp	r0, #0
   beq	earlier_than_label

Which was lost information to

   cmp	r0, #CPU_3XX_ES20
   blt	earlier_than_label

The paths through the enable routine were verified by
adding an infinite loop and seeing the hang.  Then
removing the infinite loop and seeing it continue.

The disable routine is similar enough that it was not
tested with this method.

Run tested by cold booting from nand on beagle and zoom1.
Compile tested on MAKEALL arm.

Signed-off-by: Tom Rix &lt;Tom.Rix@windriver.com&gt;
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<pre>
v7_flush_dcache_all, because it depends on omap ROM code is not
generic.  Rename the function to 'invalidate_dcache' and move it
to the omap cpu directory.

Collect the other omap cache routines l2_cache_enable and
l2_cache_disable with invalide_dcache into cache.S.  This
means removing the old cache.c file that contained l2_cache_enable
and l2_cache_disable.

The conversion from cache.c to cache.S was done most through
disassembling the uboot binary.  The only significant change was
to change the comparision for the return of get_cpu_rev from

   cmp	r0, #0
   beq	earlier_than_label

Which was lost information to

   cmp	r0, #CPU_3XX_ES20
   blt	earlier_than_label

The paths through the enable routine were verified by
adding an infinite loop and seeing the hang.  Then
removing the infinite loop and seeing it continue.

The disable routine is similar enough that it was not
tested with this method.

Run tested by cold booting from nand on beagle and zoom1.
Compile tested on MAKEALL arm.

Signed-off-by: Tom Rix &lt;Tom.Rix@windriver.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>OMAP3 Fix compiler warning for v7_flush_dcache_all</title>
<updated>2009-07-18T20:36:32+00:00</updated>
<author>
<name>Tom Rix</name>
<email>Tom.Rix@windriver.com</email>
</author>
<published>2009-06-30T20:04:13+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6bb6e6c75ec4ef496f00f7f530e549d3e073c5de'/>
<id>6bb6e6c75ec4ef496f00f7f530e549d3e073c5de</id>
<content type='text'>
On build of omap3 targets in MAKEALL, the *.ERR files have

cpu.c: In function 'cleanup_before_linux':
cpu.c:64: warning: implicit declaration of function 'v7_flush_dcache_all'
cpu.c:64: warning: implicit declaration of function 'get_device_type

The functions v7_flush_dcache_all and get_device_type are declared
in include/asm-arm/arch-omap3/sys_proto.h, so use this file to
declare the functions.

Signed-off-by: Tom Rix &lt;Tom.Rix@windriver.com&gt;
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<pre>
On build of omap3 targets in MAKEALL, the *.ERR files have

cpu.c: In function 'cleanup_before_linux':
cpu.c:64: warning: implicit declaration of function 'v7_flush_dcache_all'
cpu.c:64: warning: implicit declaration of function 'get_device_type

The functions v7_flush_dcache_all and get_device_type are declared
in include/asm-arm/arch-omap3/sys_proto.h, so use this file to
declare the functions.

Signed-off-by: Tom Rix &lt;Tom.Rix@windriver.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Coding style cleanup; update CHANGELOG</title>
<updated>2009-07-07T20:35:02+00:00</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2009-07-07T20:35:02+00:00</published>
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<id>8e5e9b940cdede0debe528cdd7edccccbb3ebf2a</id>
<content type='text'>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
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<pre>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
</pre>
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</content>
</entry>
<entry>
<title>move L2 cache enable/disable function to cache.c in the omap3 SoC directory</title>
<updated>2009-07-06T19:52:25+00:00</updated>
<author>
<name>Kim, Heung Jun</name>
<email>riverful@gmail.com</email>
</author>
<published>2009-06-20T09:02:17+00:00</published>
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<id>06e758e75c79ce8761866bf8165c443584a20893</id>
<content type='text'>
Signed-off-by: HeungJun, Kim &lt;riverful.kim@samsung.com&gt;
CC: Dirk Behme &lt;dirk.behme@googlemail.com&gt;
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD &lt;plagnioj@jcrosoft.com&gt;
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<pre>
Signed-off-by: HeungJun, Kim &lt;riverful.kim@samsung.com&gt;
CC: Dirk Behme &lt;dirk.behme@googlemail.com&gt;
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD &lt;plagnioj@jcrosoft.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>arm: remove cpu_init</title>
<updated>2009-06-12T18:39:52+00:00</updated>
<author>
<name>Jean-Christophe PLAGNIOL-VILLARD</name>
<email>plagnioj@jcrosoft.com</email>
</author>
<published>2009-05-09T11:21:19+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ad7e8aac6920f8b8a85b3cc2e93bca7458e99aa1'/>
<id>ad7e8aac6920f8b8a85b3cc2e93bca7458e99aa1</id>
<content type='text'>
move s3c44b0 to arch_cpu_init and as noone use cpu_init remove it

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD &lt;plagnioj@jcrosoft.com&gt;
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<pre>
move s3c44b0 to arch_cpu_init and as noone use cpu_init remove it

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD &lt;plagnioj@jcrosoft.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>arm: unify interrupt init</title>
<updated>2009-06-12T18:39:52+00:00</updated>
<author>
<name>Jean-Christophe PLAGNIOL-VILLARD</name>
<email>plagnioj@jcrosoft.com</email>
</author>
<published>2009-05-09T11:21:18+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c358d9c3f16571e8f825e81b75eaf32e228cb669'/>
<id>c358d9c3f16571e8f825e81b75eaf32e228cb669</id>
<content type='text'>
all arm init the IRQ stack the same way
so unify it in lib_arm/interrupts.c and then call arch specific interrupt init

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD &lt;plagnioj@jcrosoft.com&gt;
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<pre>
all arm init the IRQ stack the same way
so unify it in lib_arm/interrupts.c and then call arch specific interrupt init

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD &lt;plagnioj@jcrosoft.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Fix e-mail address of Gary Jennejohn.</title>
<updated>2009-05-15T20:11:59+00:00</updated>
<author>
<name>Detlev Zundel</name>
<email>dzu@denx.de</email>
</author>
<published>2009-05-13T08:54:10+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=792a09eb9d5d8c4f74b7e9f2e887316d511a4e80'/>
<id>792a09eb9d5d8c4f74b7e9f2e887316d511a4e80</id>
<content type='text'>
Signed-off-by: Detlev Zundel &lt;dzu@denx.de&gt;
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<pre>
Signed-off-by: Detlev Zundel &lt;dzu@denx.de&gt;
</pre>
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</content>
</entry>
<entry>
<title>OMAP3: Print correct silicon revision</title>
<updated>2009-04-29T19:11:49+00:00</updated>
<author>
<name>Sanjeev Premi</name>
<email>premi@ti.com</email>
</author>
<published>2009-04-27T15:57:54+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=cba0b778dd5f1ea32959b6825c7f0a31501a99d5'/>
<id>cba0b778dd5f1ea32959b6825c7f0a31501a99d5</id>
<content type='text'>
The function display_board_info() displays incorrect
silicon revision - based on the return value from
function get_cpu_rev().

This patch fixes the problem.

Signed-off-by: Sanjeev Premi &lt;premi@ti.com&gt;
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<pre>
The function display_board_info() displays incorrect
silicon revision - based on the return value from
function get_cpu_rev().

This patch fixes the problem.

Signed-off-by: Sanjeev Premi &lt;premi@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm: unify reset command</title>
<updated>2009-04-05T11:08:03+00:00</updated>
<author>
<name>Jean-Christophe PLAGNIOL-VILLARD</name>
<email>plagnioj@jcrosoft.com</email>
</author>
<published>2009-04-05T11:08:03+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ab298231518675b3784aea88ee9b978438f99e63'/>
<id>ab298231518675b3784aea88ee9b978438f99e63</id>
<content type='text'>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD &lt;plagnioj@jcrosoft.com&gt;
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<pre>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD &lt;plagnioj@jcrosoft.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>arm: clean cache management</title>
<updated>2009-04-05T11:06:31+00:00</updated>
<author>
<name>Jean-Christophe PLAGNIOL-VILLARD</name>
<email>plagnioj@jcrosoft.com</email>
</author>
<published>2009-04-05T11:06:31+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b3acb6cd4059dfb29a5e99095d802717f53ff784'/>
<id>b3acb6cd4059dfb29a5e99095d802717f53ff784</id>
<content type='text'>
unify arm cache management except for non standard cache as ARM7TDMI

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD &lt;plagnioj@jcrosoft.com&gt;
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<pre>
unify arm cache management except for non standard cache as ARM7TDMI

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD &lt;plagnioj@jcrosoft.com&gt;
</pre>
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</content>
</entry>
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