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<title>u-boot.git/cpu/arm_cortexa8/omap3/Makefile, branch v2009.11</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/cpu/arm_cortexa8/omap3/Makefile?h=v2009.11</id>
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<updated>2009-10-13T11:17:33Z</updated>
<entry>
<title>OMAP3 Move cache routine to cache.S</title>
<updated>2009-10-13T11:17:33Z</updated>
<author>
<name>Tom Rix</name>
<email>Tom.Rix@windriver.com</email>
</author>
<published>2009-09-10T19:27:57Z</published>
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<id>urn:sha1:7a2aa8b68120f333ed2edc33475ca195810d6cb1</id>
<content type='text'>
v7_flush_dcache_all, because it depends on omap ROM code is not
generic.  Rename the function to 'invalidate_dcache' and move it
to the omap cpu directory.

Collect the other omap cache routines l2_cache_enable and
l2_cache_disable with invalide_dcache into cache.S.  This
means removing the old cache.c file that contained l2_cache_enable
and l2_cache_disable.

The conversion from cache.c to cache.S was done most through
disassembling the uboot binary.  The only significant change was
to change the comparision for the return of get_cpu_rev from

   cmp	r0, #0
   beq	earlier_than_label

Which was lost information to

   cmp	r0, #CPU_3XX_ES20
   blt	earlier_than_label

The paths through the enable routine were verified by
adding an infinite loop and seeing the hang.  Then
removing the infinite loop and seeing it continue.

The disable routine is similar enough that it was not
tested with this method.

Run tested by cold booting from nand on beagle and zoom1.
Compile tested on MAKEALL arm.

Signed-off-by: Tom Rix &lt;Tom.Rix@windriver.com&gt;
</content>
</entry>
<entry>
<title>ARM Cortex A8: Move OMAP3 specific reset handler</title>
<updated>2009-07-22T21:39:42Z</updated>
<author>
<name>Minkyu Kang</name>
<email>mk7.kang@samsung.com</email>
</author>
<published>2009-07-20T02:40:01Z</published>
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<id>urn:sha1:6b96a20d512b04a808438553874c00cf40812c44</id>
<content type='text'>
Because of the reset_cpu is soc specific, should be move to soc

Cc: Dirk Behme &lt;dirk.behme@googlemail.com&gt;
Signed-off-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</content>
</entry>
<entry>
<title>move L2 cache enable/disable function to cache.c in the omap3 SoC directory</title>
<updated>2009-07-06T19:52:25Z</updated>
<author>
<name>Kim, Heung Jun</name>
<email>riverful@gmail.com</email>
</author>
<published>2009-06-20T09:02:17Z</published>
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<id>urn:sha1:06e758e75c79ce8761866bf8165c443584a20893</id>
<content type='text'>
Signed-off-by: HeungJun, Kim &lt;riverful.kim@samsung.com&gt;
CC: Dirk Behme &lt;dirk.behme@googlemail.com&gt;
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD &lt;plagnioj@jcrosoft.com&gt;
</content>
</entry>
<entry>
<title>OMAP3 Port kernel omap gpio interface.</title>
<updated>2009-06-12T18:39:50Z</updated>
<author>
<name>Tom Rix</name>
<email>Tom.Rix@windriver.com</email>
</author>
<published>2009-05-15T21:48:36Z</published>
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<id>urn:sha1:0c872ecd01d6782ae9d37b6eb721404a4a48f356</id>
<content type='text'>
Port version 2.6.27 of the linux kernel's omap gpio interface to u-boot.
The orignal source is in linux/arch/arm/plat-omap/gpio.c

See doc/README.omap3 for instructions on use.

Signed-off-by: Tom Rix &lt;Tom.Rix@windriver.com&gt;
</content>
</entry>
<entry>
<title>arm: timer and interrupt init rework</title>
<updated>2009-06-12T18:39:48Z</updated>
<author>
<name>Jean-Christophe PLAGNIOL-VILLARD</name>
<email>plagnioj@jcrosoft.com</email>
</author>
<published>2009-05-15T21:47:02Z</published>
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<id>urn:sha1:b54384e3ba6b5535751f317fcd3940a53eed0d3a</id>
<content type='text'>
actually the timer init use the interrupt_init as init callback
which make the interrupt and timer implementation difficult to follow

so now rename it as int timer_init(void) and use interrupt_init for interrupt

btw also remane the corresponding file to the functionnality implemented

as ixp arch implement two timer - one based on interrupt - so all the timer
related code is moved to timer.c

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD &lt;plagnioj@jcrosoft.com&gt;
</content>
</entry>
<entry>
<title>OMAP3: Reorganize Makefile style</title>
<updated>2009-06-12T18:39:48Z</updated>
<author>
<name>Jean-Christophe PLAGNIOL-VILLARD</name>
<email>plagnioj@jcrosoft.com</email>
</author>
<published>2009-05-15T21:45:22Z</published>
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<id>urn:sha1:5b4bebe1d20c4f2b70d48b06aed1016785efcc25</id>
<content type='text'>
Reformat COBJS handling.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD &lt;plagnioj@jcrosoft.com&gt;
Signed-off-by: Dirk Behme &lt;dirk.behme@googlemail.com&gt;
</content>
</entry>
<entry>
<title>OMAP3: Add common cpu and start code</title>
<updated>2009-01-24T16:51:21Z</updated>
<author>
<name>Dirk Behme</name>
<email>dirk.behme@googlemail.com</email>
</author>
<published>2008-12-14T08:47:13Z</published>
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<id>urn:sha1:0b02b184003e6a5023e05d5f31de54db279b1431</id>
<content type='text'>
Add common cpu and start code.

Signed-off-by: Dirk Behme &lt;dirk.behme@googlemail.com&gt;
</content>
</entry>
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