u-boot.git/cpu/arm_cortexa8, branch v2010.03 Unnamed repository; edit this file 'description' to name the repository. Prepare v2010.03-rc1 2010-03-12T22:06:04+00:00 Wolfgang Denk wd@denx.de 2010-03-12T22:06:04+00:00 93910edb595a88d394da3eb2cf5148096155dfe9 Coding style cleanup, update CHANGELOG. Signed-off-by: Wolfgang Denk <wd@denx.de> 
Coding style cleanup, update CHANGELOG.

Signed-off-by: Wolfgang Denk <wd@denx.de>
MX51: removed warnings for the mx51evk 2010-03-07T18:36:36+00:00 Stefano Babic sbabic@denx.de 2010-03-05T16:54:37+00:00 e4d34492017c95e4041ea0c581e1ab8d1d49381b The patch removes warnings at compile time and provides some cleanup code: - Removed comment on NAND (not yet supported) from lowlevel_init.S - Removed NFMS bit definition from imx-regs.h The bit is only related to MX.25/35 and can lead to confusion - Moved is_soc_rev() to soc specific code (removed from mx51evk.c) Signed-off-by: Stefano Babic <sbabic@denx.de> 
The patch removes warnings at compile time and provides
some cleanup code:
- Removed comment on NAND (not yet supported) from lowlevel_init.S
- Removed NFMS bit definition from imx-regs.h
  The bit is only related to MX.25/35 and can lead to confusion
- Moved is_soc_rev() to soc specific code (removed from mx51evk.c)

Signed-off-by: Stefano Babic <sbabic@denx.de>
fsl_esdhc: add support for mx51 processor 2010-03-07T18:36:36+00:00 Stefano Babic sbabic@denx.de 2010-02-05T14:11:27+00:00 c67bee1460a0da89ef08cbc28375171acc9a4227 The esdhc controller in the mx51 processor is quite the same as the one in some powerpc processors (MPC83xx, MPC85xx). This patches adapts the driver to support the arm mx51. Signed-off-by: Stefano Babic <sbabic@denx.de> 
The esdhc controller in the mx51 processor is quite
the same as the one in some powerpc processors
(MPC83xx, MPC85xx). This patches adapts the driver
to support the arm mx51.

Signed-off-by: Stefano Babic <sbabic@denx.de>
MX51: Add initial support for the Freescale MX51 2010-03-07T18:36:35+00:00 Stefano Babic sbabic@denx.de 2010-01-20T17:19:32+00:00 64fdf452a85718935d82416d141be144b262c542 The patch add initial support for the Freescale i.MX51 processor (family arm cortex_a8). Signed-off-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Fred Fan <fanyefeng@gmail.com> 
The patch add initial support for the Freescale i.MX51 processor
(family arm cortex_a8).

Signed-off-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Fred Fan <fanyefeng@gmail.com>
OMAP3: workaround for ARM Cortex-A8 erratum 725233 2010-03-07T18:36:35+00:00 Siarhei Siamashka siarhei.siamashka@gmail.com 2010-02-24T04:56:36+00:00 041d42e789aba20296ffcde92173f100a9592880 725233: PLD instructions executed with PLD data forwarding enabled can result in a processor deadlock This deadlock can happen when NEON load instructions are used together with cache preload instructions (PLD). The problematic conditions can be triggered in-the-wild by NEON optimized functions from pixman library (http://cgit.freedesktop.org/pixman), which perform dynamic adjustment of prefetch distance. The workaround disables PLD data forwarding by setting PLD_FWD bit in L2 Cache Auxiliary Control Register as recommended in ARM Cortex-A8 errata list. The deadlock can only happen on r1pX revisions of Cortex-A8 (used in OMAP34xx/OMAP35xx). Performance impact of the workaround is practically non-existant. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> 
725233: PLD instructions executed with PLD data forwarding
enabled can result in a processor deadlock

This deadlock can happen when NEON load instructions are used together
with cache preload instructions (PLD). The problematic conditions
can be triggered in-the-wild by NEON optimized functions from pixman
library (http://cgit.freedesktop.org/pixman), which perform dynamic
adjustment of prefetch distance.

The workaround disables PLD data forwarding by setting PLD_FWD bit
in L2 Cache Auxiliary Control Register as recommended in ARM Cortex-A8
errata list.

The deadlock can only happen on r1pX revisions of Cortex-A8 (used in
OMAP34xx/OMAP35xx). Performance impact of the workaround is practically
non-existant.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
OMAP3: Avoid re-write to PRM_CLKSRC_CTRL 2010-02-12T18:31:54+00:00 Sanjeev Premi premi@ti.com 2010-02-08T16:33:25+00:00 b74064a0e2984a166e3575852f3697ef5595a97b In function get_osc_clk_speed(), do not change/ update the divider for SYS_CLK as it can has cascading effect on the other derived clocks. Sudden change in divider value can lead to inconsistent behavior in the system - often leading to crashes. The problem was found when working with OMAP3EVM using DM3730 processor card. The patch has been tested with OMAP3530 on OMAP3EVM as well Signed-off-by: Sanjeev Premi <premi@ti.com> Signed-off-by: Hiremath Vaibhav <hvaibhav@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> 
In function get_osc_clk_speed(), do not change/ update
the divider for SYS_CLK as it can has cascading effect
on the other derived clocks.

Sudden change in divider value can lead to inconsistent
behavior in the system - often leading to crashes.

The problem was found when working with OMAP3EVM using
DM3730 processor card.

The patch has been tested with OMAP3530 on OMAP3EVM as
well

Signed-off-by: Sanjeev Premi <premi@ti.com>
Signed-off-by: Hiremath Vaibhav <hvaibhav@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
s5pc1xx: update cache routines 2010-01-23T14:15:48+00:00 Minkyu Kang mk7.kang@samsung.com 2009-12-18T06:03:51+00:00 d8e5f55475e621e793a15d93e2dd2549c5138735 Because of v7_flush_dcache_all is moved to omap3/cache.S and s5pc110 needs cache routines, update s5pc1xx cache routines. l2_cache_enable and l2_caceh_disable are moved from cache.c to cache.S and invalidate_dcache is modified for SoC specific. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> 
Because of v7_flush_dcache_all is moved to omap3/cache.S
and s5pc110 needs cache routines, update s5pc1xx cache routines.

l2_cache_enable and l2_caceh_disable are moved from cache.c to cache.S
and invalidate_dcache is modified for SoC specific.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Merge branch 'master' into next 2009-12-07T21:47:17+00:00 Wolfgang Denk wd@denx.de 2009-12-07T21:47:17+00:00 206c00f26f56af02686cb69bfe5c75e979063171 Conflicts: lib_generic/zlib.c Signed-off-by: Wolfgang Denk <wd@denx.de> 
Conflicts:
	lib_generic/zlib.c

Signed-off-by: Wolfgang Denk <wd@denx.de>
help: Correct syntax of nandecc help output. 2009-12-07T21:06:51+00:00 Robert P. J. Day rpjday@crashcourse.ca 2009-11-17T12:30:23+00:00 a93c92cddaedd5f0720e0da15c6664f7a688b582 "nandecc" help output should not reproduce the command name, nor have a trailing newline. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca> 
"nandecc" help output should not reproduce the command name, nor have
a trailing newline.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Generic udelay() with watchdog support 2009-12-05T00:08:53+00:00 Ingo van Lil inguin@gmx.de 2009-11-24T13:09:21+00:00 3eb90bad651fab39cffba750ec4421a9c01d60e7 According to the PPC reference implementation the udelay() function is responsible for resetting the watchdog timer as frequently as needed. Most other architectures do not meet that requirement, so long-running operations might result in a watchdog reset. This patch adds a generic udelay() function which takes care of resetting the watchdog before calling an architecture-specific __udelay(). Signed-off-by: Ingo van Lil <inguin@gmx.de> 
According to the PPC reference implementation the udelay() function is
responsible for resetting the watchdog timer as frequently as needed.
Most other architectures do not meet that requirement, so long-running
operations might result in a watchdog reset.

This patch adds a generic udelay() function which takes care of
resetting the watchdog before calling an architecture-specific
__udelay().

Signed-off-by: Ingo van Lil <inguin@gmx.de>