Looks like the initcode updates fell out of order during my merges.  The
patch that really fixes up this code is part of power-on overhaul and so
is too large for merging at this point.  Instead, we can disable the code
as no currently in-tree board depends on it.  The next merge window will
fix things up properly.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Previously, booting over the UART required the baud rate to be known ahead
of time.  Using a bit of tricky simple math, we can calculate the new board
rate based on the old divisors.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Robin Getz <rgetz@blackfin.uclinux.org>

Newer Blackfin boot roms support using the fast SPI read command rather than
just the slow one.  If the functionality is available, then use it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Some bits of the DDR MMRs should not be set.  If they do, bad things may
happen (like random failures or hardware destruction).

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Newer Blackfin's have an on-chip rom with a syscontrol() function that needs
to be used to properly program the memory and voltage settings as it will
include (possibly critical) factory tested bias values.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

As pointed out by Ivan Koryakovskiy, the initialization code was not
actually respecting the CONFIG_CLKIN_HALF option when configuring the
PLL_CTL register.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

All of the duplicated code for Blackfin processors and boot modes have been
unified.  After all, the core is the same for all processors, just the
peripheral set differs (which gets handled in the drivers).

Signed-off-by: Mike Frysinger <vapier@gentoo.org>