u-boot.git/cpu/blackfin/initcode.c, branch v2009.11

Blackfin: fix booting with older bootroms (no EVT1)

2009-05-06T12:47:21+00:00

When dropping jump block support, the assumption was that all bootroms
supported entry point redirection via the EVT1 register.  Unfortunately,
this turned out to be incorrect for the oldest Blackfin parts (BF533-0.2
and older and BF561).  No one really noticed earlier because these parts
usually are booted by bypassing the bootrom entirely, and older BF533
parts are not supported at all (too many anomalies).

Signed-off-by: Mike Frysinger

Blackfin: recurse with early serial initcode

2009-05-06T12:47:16+00:00

Make sure we recurse through serial_putc() rather than bang on the UART
transmit register directly to avoid hardware overflows when using \n.

Signed-off-by: Mike Frysinger

Blackfin: add check for anomaly 05000362

2009-04-06T21:37:48+00:00

DESCRIPTION:
The column address width settings for banks 2 and 3 are misconnected in
the SDRAM controller.  Accesses to bank 2 will result in an error if the
Column Address Width for bank 3 (EB3CAW ) is not set to be the same as
that of bank 2.

WORKAROUND:
If using bank 2, make sure that banks 2 and 3 have the same column address
width settings in the EBIU_SDBCTL register.  This must be the case
regardless of whether or not bank 3 is enabled.

Signed-off-by: Mike Frysinger

Blackfin: add comment about anomaly 05000430 avoidance

2009-04-06T21:37:48+00:00

Signed-off-by: Mike Frysinger

Blackfin: add workaround for anomaly 05000242

2009-04-06T21:37:48+00:00

DESCRIPTION:
If the DF bit is set prior to a hardware reset, the PLL will continue to
divide CLKIN by 2 after the hardware reset, but the DF bit itself will be
cleared in the PLL_CTL register.

WORKAROUND:
Reprogram the PLL with DF cleared if the desire is to not divide CLKIN by
2 after reset.

Signed-off-by: Mike Frysinger

Blackfin: add workaround for anomaly 05000171

2009-04-06T21:37:47+00:00

DESCRIPTION:
The Boot ROM is executed at power up/reset and changes the value of the
SICA_IWR registers from their default reset value of 0xFFFF, but does not
restore them.

WORKAROUND:
User code should not rely on the default value of these registers.  Set
the desired values explicitly.

Signed-off-by: Mike Frysinger

Blackfin: fix crash when booting from external memory

2009-04-02T10:41:56+00:00

When testing a u-boot binary that hasn't been booted from the bootrom, we
have to make sure the bootstruct structure has sane storage space.  If we
don't, the initcode will crash when it tries to dereference an invalid
pointer.

Signed-off-by: Mike Frysinger

Blackfin: put memory into self-refresh before/after programming clocks

2009-03-23T19:14:55+00:00

When initializing the core clocks, stick external memory into self-refresh.
This gains us a few cool things:
 - support suspend-to-RAM with Linux
 - reprogram clocks automatically when doing "go" on u-boot.bin in RAM
 - make sure settings are stable before flashing new version
 - finally fully unify initialize startup code path between LDR/non-LDR

Signed-off-by: Mike Frysinger

Blackfin: do not program voltage regulator on parts that do not have one

2009-03-23T19:14:55+00:00

Some newer Blackfins (like the BF51x) do not have an on-chip voltage
regulator, so do not attempt to program the memory as if it does.

Signed-off-by: Mike Frysinger

Blackfin: setup a sane default EBIU_SDBCTL for SDRAM controllers

2009-03-23T19:14:54+00:00

If the board config does not specify an explicit EBIU_SDBCTL value, set it
up with sane values based on other configuration options.

Signed-off-by: Mike Frysinger