u-boot.git/cpu/mips, branch v1.3.3-rc2

Use jr as register jump instruction

2008-04-18T07:47:29+00:00

Current assembler codes are inconsistent in the way of register jump
instruction usage; some use jr, some use j. Of course GNU as allows both
usages, but as can be expected from `Jump Register' the mnemonic `jr' is
more intuitive than `j'. For example, Linux doesn't have `j ' usage
at all.

Signed-off-by: Shinya Kuribayashi

cpu/mips/cpu.c: Fix flush_cache bug

2008-04-17T21:54:23+00:00

Cache operations have to take line address (addr), not start_addr.
I noticed this bug when debugging ping failure.

Signed-off-by: Shinya Kuribayashi

[MIPS] Extend MIPS_MAX_CACHE_SIZE upto 64kB

2008-03-25T12:30:07+00:00

Signed-off-by: Shinya Kuribayashi

[MIPS] Fix dcache_status()

2008-03-25T12:30:07+00:00

You can't judge UNCACHED by Config.K0 LSB.

Signed-off-by: Shinya Kuribayashi

[MIPS] Introduce _machine_restart

2008-03-25T12:30:07+00:00

Handles machine specific functions by using weak functions.

Signed-off-by: Shinya Kuribayashi

[MIPS] Cleanup CP0 Status initialization

2008-03-25T12:30:07+00:00

Add setup_c0_status from Linux. For the moment we disable interrupts, set
CU0, mark the kernel mode, and clear ERL and EXL. This is good enough for
reset-time configuration and will work well across most processors.

Signed-off-by: Shinya Kuribayashi

[MIPS] Initialize CP0 Cause before setting up CP0 Status register

2008-03-25T12:30:07+00:00

Without this change, we'll be suffering from deffered WATCH exception
once Status.EXL is cleared. Make sure Cause.WP is cleared.

Signed-off-by: Shinya Kuribayashi

[MIPS] INCA-IP: Move watchdog init code from start.S to lowlevel_init()

2008-03-25T12:30:07+00:00

Move things to appropriate place.

Signed-off-by: Shinya Kuribayashi

[MIPS] Implement flush_cache()

2008-03-25T12:30:06+00:00

We do Hit_Writeback_Inv_D and Hit_Invalidate_I. You might think that you
don't need to do Hit_Invalidate_I, but flush_cache() needs it since this
function is used not only in U-Boot specfic programs but also at loading
target binaries.

Signed-off-by: Shinya Kuribayashi

[MIPS] Fix I-/D-cache initialization loops

2008-03-25T12:30:06+00:00

Currently we do 1) Index_Store_Tag_I, 2) Fill and 3) Index_Store_Tag_I
again per a loop for I-cache initialization. But according to 'See MIPS
Run', we're encouraged to use three separate loops rather than combining
them *for both I- and D-cache*. This patch tries to fix this.

In accordance with fixing above, mips_init_[id]cache are separated from
mips_cache_reset(), and rewrite cache loops are completely rewritten with
useful macros.

Signed-off-by: Shinya Kuribayashi