u-boot.git/cpu/mpc83xx/cpu_init.c, branch u-boot-2009.11.y

mpc83xx: boot time regression, move LCRR setup back to cpu_init_f

2009-12-09T17:40:52+00:00

Commit c7190f02 (retain POR values of non-configured ACR, SPCR, SCCR,
and LCRR bitfields) moved the LCRR assignment to after relocation
to RAM because of the potential problem with changing the local bus
clock while executing from flash.

This change unfortunately adversely affects the boot time, as running
all code up to cpu_init_r can cause significant slowdown.

E.G. on a 8347 board a bootup time increase of ~600ms has been observed:

   0.020 CPU:   e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz
   0.168 RS:    232
   0.172 I2C:   ready
   0.176 DRAM:  64 MB
   1.236 FLASH: 32 MB

Versus:

   0.016 CPU:   e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz
   0.092 RS:    232
   0.092 I2C:   ready
   0.096 DRAM:  64 MB
   0.644 FLASH: 32 MB

So far no boards have needed the late LCRR setup, so simply revert it
for now - If it is needed at a later time, those boards can either do
their own final LCRR setup in board code (E.G. in board_early_init_r),
or we can introduce a CONFIG_SYS_LCRR_LATE config option to only do
the setup in cpu_init_r.

Signed-off-by: Peter Korsgaard 
Signed-off-by: Kim Phillips

mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields

2009-09-27T02:19:38+00:00

some LCRR bits are not documented throughout the 83xx family RMs.
New board porters copying similar board configurations might omit
setting e.g., DBYP since it was not documented in their SoC's RM.

Prevent them bricking their board by retaining power on reset values
in bit fields that the board porter doesn't explicitly configure
via CONFIG_SYS__ assignments in the board
config file.

also move LCRR assignment to cpu_init_r[am] to help ensure no
transactions are being executed via the local bus while CLKDIV is being
modified.

also start to use i/o accessors.

Signed-off-by: Kim Phillips

usb: mpc834x: added support of the MPH USB controller in addition to the DR one

2009-07-14T19:53:52+00:00

Signed-off-by: Valeriy Glushkov 
Signed-off-by: Kim Phillips

mpc83xx: USB: fix: access of ehci struct elements

2009-07-09T19:33:15+00:00

It fixes the access to the 'ehci' struct elements for mpc83xx which
should have been taken care of in 4ef01010aa4799c759d75e67007fdd3a38c88c8a
Sorry about that.

Signed-off-by: Vivek Mahajan 
Signed-off-by: Remy Bohmer

mpc83xx: USB: Reorganized its support

2009-06-12T18:47:17+00:00

The following patch reorganizes/reworks the USB support for mpc83xx
as under:-

  * Moves the 83xx USB clock init from drivers/usb/host/ehci-fsl.c to
    cpu/mpx83xx/cpu_init.c

  * Board specific usb_phy_type is read from the environment

  * Adds USB EHCI specific structure in include/usb/ehci-fsl.h

  * Copyrights revamped in most of the following files

Signed-off-by: Vivek Mahajan 
Signed-off-by: Remy Bohmer

83xx: Replace CONFIG_MPC83[0-9]X with MPC83[0-9]x

2009-06-12T18:47:17+00:00

Use the standard lowercase "x" capitalization that other Freescale
architectures use for CPU defines to prevent confusion and errors

Signed-off-by: Peter Tyser 
Signed-off-by: Kim Phillips

mpc83xx: correctly set encryption and I2C bus 0 clock

2009-03-14T22:43:58+00:00

This patch makes sure the correct mask is applied when setting
the encryption and I2C bus 0 clock in SCCR.
Failing to do so may lead to ENCCM being 0 in which case I2C bus 0
won't function.

Signed-off-by: Norbert van Bolhuis 
Signed-off-by: Kim Phillips

rename CFG_ macros to CONFIG_SYS

2008-10-18T19:54:03+00:00

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD

mpc83xx: Store and display Arbiter Event Register values

2008-09-03T21:06:57+00:00

Record the Arbiter Event Register values and optionally display them.

The Arbiter Event Register can record the type and effective address of
an arbiter error, even through an HRESET. This patch stores the values in
the global data structure.

Display of the Arbiter Event registers immediately after the RSR value
can be enabled with defines. The Arbiter values will only be displayed
if an arbiter event has occured since the last Power On Reset, and either
of the following defines exist:
 #define CONFIG_DISPLAY_AER_BRIEF - display only the arbiter address and
                                    and type register values
 #define CONFIG_DISPLAY_AER_FULL  - display and interpret the arbiter
                                    event register values

Address Only transactions are one of the trapped events that can register
as an arbiter event. They occur with some cache manipulation instructions
if the HID0_ABE (Address Broadcast Enable) is set and the memory region
has the MEMORY_COHERENCE WIMG bit set. Setting:
 #define CONFIG_MASK_AER_AO - prevents the arbiter from recording address
                              only events, so that it can still capture
                              other real problems.

Signed-off-by: Nick Spence 
Signed-off-by: Kim Phillips

MPC83XX: Fix GPIO configuration - set gpio level before direction

2008-09-03T21:06:46+00:00

Set DAT value before DIR values to avoid creating glitches on the
GPIO signals.

Set gpio level register before direction register to inhibit
glitches on high level output pins.

Dir and data gets cleared at powerup, so high level output lines see
a short low pulse between setting the direction and level registers.

Issue was seen on a new board with the nReset line of the NOR flash
connected to a GPIO. Setting the direction register puts the NOR flash
in reset so the next instruction to set the level cannot get executed.

Signed-off-by: Nick Spence 
Signed-off-by: Peter Korsgaard 
Signed-off-by: Kim Phillips