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<title>u-boot.git/cpu/mpc83xx/cpu_init.c, branch v1.3.1</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/cpu/mpc83xx/cpu_init.c?h=v1.3.1</id>
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<updated>2007-08-10T06:12:03Z</updated>
<entry>
<title>mpc83xx: Add support for the display of reset status</title>
<updated>2007-08-10T06:12:03Z</updated>
<author>
<name>Dave Liu</name>
<email>daveliu@freescale.com</email>
</author>
<published>2007-06-25T02:41:56Z</published>
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<id>urn:sha1:9be39a67c9f8fef7107f5df09d673005f04d0963</id>
<content type='text'>
83xx processor family has many reset sources, such as
power on reset, software hard reset, software soft reset,
JTAG, bus monitor, software watchdog, check stop reset,
external hard reset, external software reset.
sometimes, to figure out the fault of system, we need to
know the cause of reset early before the prompt of
u-boot present.

Signed-off-by: Dave Liu &lt;daveliu@freescale.com&gt;
Signed-off-by: Kim Phillips &lt;kim.phillips@freescale.com&gt;
</content>
</entry>
<entry>
<title>Update SCCR programming in cpu_init_f() to support all 83xx processors</title>
<updated>2007-08-10T06:12:03Z</updated>
<author>
<name>Timur Tabi</name>
<email>timur@freescale.com</email>
</author>
<published>2007-07-03T18:04:34Z</published>
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<id>urn:sha1:df33f6b4d6d63693dd9200808b242de1b86cb8e8</id>
<content type='text'>
Update the cpu_init_f() function in cpu/mpc83xx/cpu_init.c to program the
bitfields for all 83xx processors.  The code to update some bitfields was
compiled only on some processors.  Now, the bitfields are programmed as long
as the corresponding CFG_SCCR option is defined in the board header file.
This means that the board header file should not define any CFG_SCCR macros
for bitfields that don't exist on that processor, otherwise the SCCR will be
programmed incorrectly.

Signed-off-by: Timur Tabi &lt;timur@freescale.com&gt;
Signed-off-by: Kim Phillips &lt;kim.phillips@freescale.com&gt;
</content>
</entry>
<entry>
<title>mpc83xx: Fix config of Arbiter, System Priority, and Clock Mode</title>
<updated>2007-03-02T20:08:26Z</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2007-02-28T05:51:42Z</published>
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<id>urn:sha1:4feab4de7bfc2cb2fed36ad76f93c3a69659bbaf</id>
<content type='text'>
The config value for:
* CFG_ACR_PIPE_DEP
* CFG_ACR_RPTCNT
* CFG_SPCR_TSEC1EP
* CFG_SPCR_TSEC2EP
* CFG_SCCR_TSEC1CM
* CFG_SCCR_TSEC2CM

Were not being used when setting the appropriate register

Added:
* CFG_SCCR_USBMPHCM
* CFG_SCCR_USBDRCM
* CFG_SCCR_PCICM
* CFG_SCCR_ENCCM

To allow full config of the SCCR.

Also removed random CFG_SCCR settings in MPC8349EMDS, TQM834x, and sbc8349
that were just bogus.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
</entry>
<entry>
<title>mpc83xx: Add support for the MPC832XEMDS board</title>
<updated>2007-03-02T17:05:53Z</updated>
<author>
<name>Dave Liu</name>
<email>r63238@freescale.com</email>
</author>
<published>2006-12-07T13:13:15Z</published>
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<id>urn:sha1:24c3aca3f1358b113d3215adb5433b156e99f72b</id>
<content type='text'>
This patch supports DUART, ETH3/4 and PCI etc.

Signed-off-by: Dave Liu &lt;daveliu@freescale.com&gt;
</content>
</entry>
<entry>
<title>mpc83xx: streamline the 83xx immr head file</title>
<updated>2007-03-02T17:05:53Z</updated>
<author>
<name>Dave Liu</name>
<email>r63238@freescale.com</email>
</author>
<published>2006-12-07T13:11:58Z</published>
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<id>urn:sha1:e080313c32322e15ab5a18eb896a252858c57284</id>
<content type='text'>
For better format and style, I streamlined the 83xx head files,
including immap_83xx.h and mpc83xx.h. In the old head files, 1)
duplicated macro definition appear in the both files; 2) the structure
of QE immr is duplicated in the immap_83xx.h and immap_qe.h; 3) The
macro definition put inside the each structure. So, I cleaned up the
structure of QE immr from immap_83xx.h, deleted the duplicated stuff and
moved the macro definition to mpc83xx.h, Just like MPC8260.

CHANGELOG

*streamline the 83xx immr head file

Signed-off-by: Dave Liu &lt;daveliu@freescale.com&gt;
</content>
</entry>
<entry>
<title>mpc83xx: Miscellaneous code style fixes</title>
<updated>2006-11-29T05:34:30Z</updated>
<author>
<name>Timur Tabi</name>
<email>timur@freescale.com</email>
</author>
<published>2006-11-28T18:09:35Z</published>
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<id>urn:sha1:e857a5bdb3954b896c0920cb9d8d2b1b9c107ce5</id>
<content type='text'>
Implement various code style fixes and similar changes.

Signed-off-by: Timur Tabi &lt;timur@freescale.com&gt;
</content>
</entry>
<entry>
<title>mpc83xx: Replace CFG_IMMRBAR with CFG_IMMR</title>
<updated>2006-11-04T01:42:23Z</updated>
<author>
<name>Timur Tabi</name>
<email>timur@freescale.com</email>
</author>
<published>2006-11-03T18:00:28Z</published>
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<id>urn:sha1:d239d74b1c937984bc519083a8e7de373a390f06</id>
<content type='text'>
Replace all instances of CFG_IMMRBAR with CFG_IMMR, so that the 83xx
tree matches the other 8xxx trees.

Signed-off-by: Timur Tabi &lt;timur@freescale.com&gt;
</content>
</entry>
<entry>
<title>mpc83xx: add QE ethernet support</title>
<updated>2006-11-04T01:42:21Z</updated>
<author>
<name>Dave Liu</name>
<email>daveliu@freescale.com</email>
</author>
<published>2006-11-03T18:11:15Z</published>
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<id>urn:sha1:7737d5c658c606f999dfbe3e86b0fed49e5c50ef</id>
<content type='text'>
this patch adds support for the QUICC Engine based UCC gigabit ethernet device.
</content>
</entry>
<entry>
<title>mpc83xx: Add support for the MPC8349E-mITX</title>
<updated>2006-11-04T01:42:20Z</updated>
<author>
<name>Timur Tabi</name>
<email>timur@freescale.com</email>
</author>
<published>2006-11-01T00:44:42Z</published>
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<id>urn:sha1:2ad6b513b31070bd0c003792ed1c3e7f5d740357</id>
<content type='text'>
PREREQUISITE PATCHES:

* This patch can only be applied after the following patches have been applied:

  1) DNX#2006090742000024 "Add support for multiple I2C buses"
  2) DNX#2006090742000033 "Multi-bus I2C implementation of MPC834x"
  3) DNX#2006091242000041 "Additional MPC8349 support for multibus i2c"
  4) DNX#2006091242000078 "Add support for variable flash memory sizes on 83xx systems"
  5) DNX#2006091242000069 "Add support for Errata DDR6 on MPC 834x systems"

CHANGELOG:

* Add support for the Freescale MPC8349E-mITX reference design platform.
  The second TSEC (Vitesse 7385 switch) is not supported at this time.

Signed-off-by: Timur Tabi &lt;timur@freescale.com&gt;
</content>
</entry>
<entry>
<title>GCC-4.x fixes: clean up global data pointer initialization for all boards.</title>
<updated>2006-03-31T16:32:53Z</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@pollux.denx.de</email>
</author>
<published>2006-03-31T16:32:53Z</published>
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<id>urn:sha1:d87080b721e4f8dca977af7571c5338ae7bb8db7</id>
<content type='text'>
</content>
</entry>
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