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<title>u-boot.git/cpu/mpc83xx/cpu_init.c, branch v2009.08</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>usb: mpc834x: added support of the MPH USB controller in addition to the DR one</title>
<updated>2009-07-14T19:53:52+00:00</updated>
<author>
<name>Valeriy Glushkov</name>
<email>gvv@lstec.com</email>
</author>
<published>2009-06-30T12:48:40+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d89e1c36891de793a20a929282acc0fc7b98feac'/>
<id>d89e1c36891de793a20a929282acc0fc7b98feac</id>
<content type='text'>
Signed-off-by: Valeriy Glushkov &lt;gvv@lstec.com&gt;
Signed-off-by: Kim Phillips &lt;kim.phillips@freescale.com&gt;
</content>
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<pre>
Signed-off-by: Valeriy Glushkov &lt;gvv@lstec.com&gt;
Signed-off-by: Kim Phillips &lt;kim.phillips@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mpc83xx: USB: fix: access of ehci struct elements</title>
<updated>2009-07-09T19:33:15+00:00</updated>
<author>
<name>Vivek Mahajan</name>
<email>vivek.mahajan@freescale.com</email>
</author>
<published>2009-06-24T04:38:40+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=db7b43e4681f6f93c336132708157a8a0cca1f8b'/>
<id>db7b43e4681f6f93c336132708157a8a0cca1f8b</id>
<content type='text'>
It fixes the access to the 'ehci' struct elements for mpc83xx which
should have been taken care of in 4ef01010aa4799c759d75e67007fdd3a38c88c8a
Sorry about that.

Signed-off-by: Vivek Mahajan &lt;vivek.mahajan@freescale.com&gt;
Signed-off-by: Remy Bohmer &lt;linux@bohmer.net&gt;
</content>
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<pre>
It fixes the access to the 'ehci' struct elements for mpc83xx which
should have been taken care of in 4ef01010aa4799c759d75e67007fdd3a38c88c8a
Sorry about that.

Signed-off-by: Vivek Mahajan &lt;vivek.mahajan@freescale.com&gt;
Signed-off-by: Remy Bohmer &lt;linux@bohmer.net&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mpc83xx: USB: Reorganized its support</title>
<updated>2009-06-12T18:47:17+00:00</updated>
<author>
<name>Vivek Mahajan</name>
<email>vivek.mahajan@freescale.com</email>
</author>
<published>2009-05-25T11:53:16+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4ef01010aa4799c759d75e67007fdd3a38c88c8a'/>
<id>4ef01010aa4799c759d75e67007fdd3a38c88c8a</id>
<content type='text'>
The following patch reorganizes/reworks the USB support for mpc83xx
as under:-

  * Moves the 83xx USB clock init from drivers/usb/host/ehci-fsl.c to
    cpu/mpx83xx/cpu_init.c

  * Board specific usb_phy_type is read from the environment

  * Adds USB EHCI specific structure in include/usb/ehci-fsl.h

  * Copyrights revamped in most of the following files

Signed-off-by: Vivek Mahajan &lt;vivek.mahajan@freescale.com&gt;
Signed-off-by: Remy Bohmer &lt;linux@bohmer.net&gt;
</content>
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<pre>
The following patch reorganizes/reworks the USB support for mpc83xx
as under:-

  * Moves the 83xx USB clock init from drivers/usb/host/ehci-fsl.c to
    cpu/mpx83xx/cpu_init.c

  * Board specific usb_phy_type is read from the environment

  * Adds USB EHCI specific structure in include/usb/ehci-fsl.h

  * Copyrights revamped in most of the following files

Signed-off-by: Vivek Mahajan &lt;vivek.mahajan@freescale.com&gt;
Signed-off-by: Remy Bohmer &lt;linux@bohmer.net&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>83xx: Replace CONFIG_MPC83[0-9]X with MPC83[0-9]x</title>
<updated>2009-06-12T18:47:17+00:00</updated>
<author>
<name>Peter Tyser</name>
<email>ptyser@xes-inc.com</email>
</author>
<published>2009-05-22T22:23:25+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2c7920afaf96d9779304202cd8a355b4f7576a83'/>
<id>2c7920afaf96d9779304202cd8a355b4f7576a83</id>
<content type='text'>
Use the standard lowercase "x" capitalization that other Freescale
architectures use for CPU defines to prevent confusion and errors

Signed-off-by: Peter Tyser &lt;ptyser@xes-inc.com&gt;
Signed-off-by: Kim Phillips &lt;kim.phillips@freescale.com&gt;
</content>
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<pre>
Use the standard lowercase "x" capitalization that other Freescale
architectures use for CPU defines to prevent confusion and errors

Signed-off-by: Peter Tyser &lt;ptyser@xes-inc.com&gt;
Signed-off-by: Kim Phillips &lt;kim.phillips@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mpc83xx: correctly set encryption and I2C bus 0 clock</title>
<updated>2009-03-14T22:43:58+00:00</updated>
<author>
<name>Norbert van Bolhuis</name>
<email>nvbolhuis@aimvalley.nl</email>
</author>
<published>2009-03-13T07:58:14+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b581626c1e2474a3dadf69d4f0e0582eccbc4235'/>
<id>b581626c1e2474a3dadf69d4f0e0582eccbc4235</id>
<content type='text'>
This patch makes sure the correct mask is applied when setting
the encryption and I2C bus 0 clock in SCCR.
Failing to do so may lead to ENCCM being 0 in which case I2C bus 0
won't function.

Signed-off-by: Norbert van Bolhuis &lt;nvbolhuis@aimvalley.nl&gt;
Signed-off-by: Kim Phillips &lt;kim.phillips@freescale.com&gt;
</content>
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<pre>
This patch makes sure the correct mask is applied when setting
the encryption and I2C bus 0 clock in SCCR.
Failing to do so may lead to ENCCM being 0 in which case I2C bus 0
won't function.

Signed-off-by: Norbert van Bolhuis &lt;nvbolhuis@aimvalley.nl&gt;
Signed-off-by: Kim Phillips &lt;kim.phillips@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>rename CFG_ macros to CONFIG_SYS</title>
<updated>2008-10-18T19:54:03+00:00</updated>
<author>
<name>Jean-Christophe PLAGNIOL-VILLARD</name>
<email>plagnioj@jcrosoft.com</email>
</author>
<published>2008-10-16T13:01:15+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6d0f6bcf337c5261c08fabe12982178c2c489d76'/>
<id>6d0f6bcf337c5261c08fabe12982178c2c489d76</id>
<content type='text'>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD &lt;plagnioj@jcrosoft.com&gt;
</content>
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<pre>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD &lt;plagnioj@jcrosoft.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mpc83xx: Store and display Arbiter Event Register values</title>
<updated>2008-09-03T21:06:57+00:00</updated>
<author>
<name>Nick Spence</name>
<email>nick.spence@freescale.com</email>
</author>
<published>2008-08-28T21:09:19+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=46497056ae3b1e81e736e9cf3a170472c5d9719f'/>
<id>46497056ae3b1e81e736e9cf3a170472c5d9719f</id>
<content type='text'>
Record the Arbiter Event Register values and optionally display them.

The Arbiter Event Register can record the type and effective address of
an arbiter error, even through an HRESET. This patch stores the values in
the global data structure.

Display of the Arbiter Event registers immediately after the RSR value
can be enabled with defines. The Arbiter values will only be displayed
if an arbiter event has occured since the last Power On Reset, and either
of the following defines exist:
 #define CONFIG_DISPLAY_AER_BRIEF - display only the arbiter address and
                                    and type register values
 #define CONFIG_DISPLAY_AER_FULL  - display and interpret the arbiter
                                    event register values

Address Only transactions are one of the trapped events that can register
as an arbiter event. They occur with some cache manipulation instructions
if the HID0_ABE (Address Broadcast Enable) is set and the memory region
has the MEMORY_COHERENCE WIMG bit set. Setting:
 #define CONFIG_MASK_AER_AO - prevents the arbiter from recording address
                              only events, so that it can still capture
                              other real problems.

Signed-off-by: Nick Spence &lt;nick.spence@freescale.com&gt;
Signed-off-by: Kim Phillips &lt;kim.phillips@freescale.com&gt;
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Record the Arbiter Event Register values and optionally display them.

The Arbiter Event Register can record the type and effective address of
an arbiter error, even through an HRESET. This patch stores the values in
the global data structure.

Display of the Arbiter Event registers immediately after the RSR value
can be enabled with defines. The Arbiter values will only be displayed
if an arbiter event has occured since the last Power On Reset, and either
of the following defines exist:
 #define CONFIG_DISPLAY_AER_BRIEF - display only the arbiter address and
                                    and type register values
 #define CONFIG_DISPLAY_AER_FULL  - display and interpret the arbiter
                                    event register values

Address Only transactions are one of the trapped events that can register
as an arbiter event. They occur with some cache manipulation instructions
if the HID0_ABE (Address Broadcast Enable) is set and the memory region
has the MEMORY_COHERENCE WIMG bit set. Setting:
 #define CONFIG_MASK_AER_AO - prevents the arbiter from recording address
                              only events, so that it can still capture
                              other real problems.

Signed-off-by: Nick Spence &lt;nick.spence@freescale.com&gt;
Signed-off-by: Kim Phillips &lt;kim.phillips@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MPC83XX: Fix GPIO configuration - set gpio level before direction</title>
<updated>2008-09-03T21:06:46+00:00</updated>
<author>
<name>Nick Spence</name>
<email>nick.spence@freescale.com</email>
</author>
<published>2008-08-23T06:52:50+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d9fe88173cb4f7d293796ffe10c7a0d3d426d8f9'/>
<id>d9fe88173cb4f7d293796ffe10c7a0d3d426d8f9</id>
<content type='text'>
Set DAT value before DIR values to avoid creating glitches on the
GPIO signals.

Set gpio level register before direction register to inhibit
glitches on high level output pins.

Dir and data gets cleared at powerup, so high level output lines see
a short low pulse between setting the direction and level registers.

Issue was seen on a new board with the nReset line of the NOR flash
connected to a GPIO. Setting the direction register puts the NOR flash
in reset so the next instruction to set the level cannot get executed.

Signed-off-by: Nick Spence &lt;nick.spence@freescale.com&gt;
Signed-off-by: Peter Korsgaard &lt;jacmet@sunsite.dk&gt;
Signed-off-by: Kim Phillips &lt;kim.phillips@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Set DAT value before DIR values to avoid creating glitches on the
GPIO signals.

Set gpio level register before direction register to inhibit
glitches on high level output pins.

Dir and data gets cleared at powerup, so high level output lines see
a short low pulse between setting the direction and level registers.

Issue was seen on a new board with the nReset line of the NOR flash
connected to a GPIO. Setting the direction register puts the NOR flash
in reset so the next instruction to set the level cannot get executed.

Signed-off-by: Nick Spence &lt;nick.spence@freescale.com&gt;
Signed-off-by: Peter Korsgaard &lt;jacmet@sunsite.dk&gt;
Signed-off-by: Kim Phillips &lt;kim.phillips@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fix system config overwrite @ MPC834x and MPC8313</title>
<updated>2008-06-25T22:04:28+00:00</updated>
<author>
<name>Andre Schwarz</name>
<email>andre.schwarz@matrix-vision.de</email>
</author>
<published>2008-06-23T09:40:56+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=846f1574ddddeda2bc227655e687308695f41cdc'/>
<id>846f1574ddddeda2bc227655e687308695f41cdc</id>
<content type='text'>
During 83xx setup the "System I/O configuration register high" gets
overwritten with user defined value if CFG_SICRH is defined.

Regarding to the MPC834x manual (Table 5-28 reve.1) bits 28+29 of SICRH
must keep their reset value regardless of configuration.

On my board (using RGMII) those bits are set after reset - yet it's
unclear where they come from.

The patch keeps both bits on MPC834x and MPC8313.

Signed-off-by: Andre Schwarz &lt;andre.schwarz@matrix-vision.de&gt;
Signed-off-by: Kim Phillips &lt;kim.phillips@freescale.com&gt;
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
During 83xx setup the "System I/O configuration register high" gets
overwritten with user defined value if CFG_SICRH is defined.

Regarding to the MPC834x manual (Table 5-28 reve.1) bits 28+29 of SICRH
must keep their reset value regardless of configuration.

On my board (using RGMII) those bits are set after reset - yet it's
unclear where they come from.

The patch keeps both bits on MPC834x and MPC8313.

Signed-off-by: Andre Schwarz &lt;andre.schwarz@matrix-vision.de&gt;
Signed-off-by: Kim Phillips &lt;kim.phillips@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Big white-space cleanup.</title>
<updated>2008-05-20T22:14:08+00:00</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2008-05-20T14:00:29+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=53677ef18e25c97ac613349087c5cb33ae5a2741'/>
<id>53677ef18e25c97ac613349087c5cb33ae5a2741</id>
<content type='text'>
This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).

Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.

Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).

Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.

Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
</pre>
</div>
</content>
</entry>
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