u-boot.git/cpu/mpc83xx, branch master

ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU

2010-04-13T07:13:16+00:00

Signed-off-by: Peter Tyser

Bug: do_reset issued via netconsole does not reset mpc83xx cpu.

2010-02-19T00:25:09+00:00

The do_reset routine in the cpu/mpc83xx/cpu.c file does not reset
the mpc83xx cpu when issued via netconsole.

Moving the console output "resetting the board." to the beginning of
the routine before disabling interrupts solved the problem.

Signed-off-by: Michael Zaidman 
Acked-by: Detlev Zundel 
Signed-off-by: Kim Phillips

kgdb: cpu/mpc* cpu/74xx: include kgdb.h when needed

2010-02-08T21:05:42+00:00

Commit cbb0cab1d929839d broke some platforms which used kgdb code but
didn't actually include kgdb.h.  So include kgdb.h in all the relevant
traps code.

Signed-off-by: Mike Frysinger

ppc: remove -ffixed-r14 gcc option.

2010-01-26T18:30:16+00:00

This is no loger needed, free up r14 for general usage.

Signed-off-by: Joakim Tjernlund

ppc: Use r12 instead of r14 as GOT pointer.

2010-01-26T18:30:13+00:00

r14 is not supposed to be clobbered by functions. Switch
to r12 and call GET_GOT when needed. This will allow u-boot
to loose the -ffixed-r14 gcc option.

Signed-off-by: Joakim Tjernlund

ppc: Loose GOT access in IRQ

2010-01-26T18:30:12+00:00

Using the GOT in IRQ handlers requires r14 to be -ffixed-r14.
Avoid this by relocatate transfer_to_handler too.
This will allow to free up r14 later on.

Signed-off-by: Joakim Tjernlund

mpc83xx: add support configure bus parking

2010-01-08T00:39:42+00:00

Add support to configure bus parking mode and master in bus arbitration
configuration (ACR). Add this for the kmeter1 port:

Configure bus arbiter with recommended values from Freescale
to improve bus latency/throughput for application with
intensive QuiccEngine activity.

Signed-off-by: Heiko Schocher 
Signed-off-by: Kim Phillips

mpc83xx: spd_sdram.c: Disable memory controller before initializing

2010-01-08T00:34:30+00:00

The memory controller could already be enabled, when spd_sdram() is
called. This could be the case for example, when the SDRAM is initialized
by the JTAG debugger.

The "sync" after the register access via the accessor function is
still needed, because the macro uses the sync before the real write
is done. So until not all accesses are converted to using accessor
functions, this sync still needs to be made "manually" here.

Signed-off-by: Stefan Roese 
Cc: Reinhard Arlt 
Acked-by: Dave Liu 
Signed-off-by: Kim Phillips

mpc83xx: boot time regression, move LCRR setup back to cpu_init_f

2009-12-09T17:40:52+00:00

Commit c7190f02 (retain POR values of non-configured ACR, SPCR, SCCR,
and LCRR bitfields) moved the LCRR assignment to after relocation
to RAM because of the potential problem with changing the local bus
clock while executing from flash.

This change unfortunately adversely affects the boot time, as running
all code up to cpu_init_r can cause significant slowdown.

E.G. on a 8347 board a bootup time increase of ~600ms has been observed:

   0.020 CPU:   e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz
   0.168 RS:    232
   0.172 I2C:   ready
   0.176 DRAM:  64 MB
   1.236 FLASH: 32 MB

Versus:

   0.016 CPU:   e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz
   0.092 RS:    232
   0.092 I2C:   ready
   0.096 DRAM:  64 MB
   0.644 FLASH: 32 MB

So far no boards have needed the late LCRR setup, so simply revert it
for now - If it is needed at a later time, those boards can either do
their own final LCRR setup in board code (E.G. in board_early_init_r),
or we can introduce a CONFIG_SYS_LCRR_LATE config option to only do
the setup in cpu_init_r.

Signed-off-by: Peter Korsgaard 
Signed-off-by: Kim Phillips

mpc83xx: mpc8313 - handle erratum IPIC1 (TSEC IRQ number swappage)

2009-10-16T22:08:35+00:00

mpc8313e erratum IPIC1 swapped TSEC interrupt ID numbers on rev. 1
h/w (see AN3545).  The base device tree in use has rev. 1 ID numbers,
so if on Rev. 2 (and higher) h/w, we fix them up here.

Signed-off-by: Kim Phillips 
Reviewed-by: Roland Lezuo