u-boot.git/cpu/mpc85xx/Makefile, branch master

ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU

2010-04-13T07:13:16+00:00

Signed-off-by: Peter Tyser

85xx: Added various P1012/P1013/P1021/P1022 defines

2010-04-07T05:21:22+00:00

There are various locations that we have chip specific info:

* Makefile for which ddr code to build
* Added P1012/P1013/P1021/P1022 to cpu_type_list and SVR list
* Added number of LAWs for P1012/P1013/P1021/P1022
* Set CONFIG_MAX_CPUS to 2 for P1021/P1022
* PCI port config

Signed-off-by: Haiying Wang 
Signed-off-by: Srikanth Srinivasan 
Signed-off-by: Kumar Gala

ppc/p4080: Add various p4080 related defines (and p4040)

2009-09-24T17:05:28+00:00

There are various locations that we have chip specific info:

* Makefile for which ddr code to build
* Added p4080 & p4040 to cpu_type_list and SVR list
* Added number of LAWs for p4080
* Set CONFIG_MAX_CPUS to 8 for p4080

Signed-off-by: Kumar Gala

ppc/85xx: Split out cpu_init_early into its own file for NAND_SPL

2009-09-16T02:30:09+00:00

By pulling out cpu_init_early we can build just it and not all of
cpu_init for NAND_SPL.

Signed-off-by: Kumar Gala

ppc/85xx: Cleanup makefile and related optional files

2009-09-08T14:10:07+00:00

Cleaned up cpu/mpc85xx/Makefile to use CONFIG_* for those obvious cases
we have like PCI, CPM2, QE.  Also reworked it to use one line per file
for everything and sorted in alphabetical order.

Signed-off-by: Kumar Gala

85xx: Added single core members of FSL P1xx/P2xx processors series

2009-08-28T22:12:41+00:00

P1011 - Single core variant of P1020
P2010 - Single core variant of P2020

Signed-off-by: Poonam Aggrwal 
Signed-off-by: Kumar Gala

85xx: Added P1020 Processor Support.

2009-08-28T22:12:39+00:00

P1020 is another member of QorIQ series of processors which falls in ULE
category. It is an e500 based dual core SOC.

Being a scaled down version of P2020 it has following differences:
- 533MHz - 800MHz core frequency.
- 256Kbyte L2 cache
- Ethernet controllers with classification capabilities.
Also the SOC is pin compatible with P2020

Signed-off-by: Poonam Aggrwal 
Signed-off-by: Kumar Gala

MPC85xx: Add MPC8569 CPU support

2009-03-30T18:33:51+00:00

There is a workaround for MPC8569 CPU Errata, which needs to set Bit 13 of
LBCR in 4K bootpage. We setup a temp TLB for eLBC controller in bootpage,
then invalidate it after LBCR bit 13 is set.

Signed-off-by: Haiying Wang 
Signed-off-by: Kumar Gala

mpc85xx: Add support for the P2020

2009-02-17T00:05:55+00:00

Added various p2020 processor specific details:
* SVR for p2020, p2020E
* immap updates for LAWs and DDR on p2020
* LAW defines related to p2020

Signed-off-by: Srikanth Srinivasan 
Signed-off-by: Travis Wheatley 
Signed-off-by: Kumar Gala

mpc85xx: Add support for the MPC8536

2008-08-27T16:43:54+00:00

The MPC8536 Adds SDHC and SATA controllers to the PQ3 family.  We
also have SERDES init code for the 8536.

Signed-off-by: Kumar Gala 
Signed-off-by: Srikanth Srinivasan 
Signed-off-by: Dejan Minic 
Signed-off-by: Jason Jin 
Signed-off-by: Dave Liu