u-boot.git/cpu/mpc85xx/cpu.c, branch master

ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU

2010-04-13T07:13:16+00:00

Signed-off-by: Peter Tyser

ppc/p4080: Determine various chip frequencies on CoreNet platforms

2009-09-24T17:05:29+00:00

The means to determine the core, bus, and DDR frequencies are completely
new on CoreNet style platforms.  Additionally on p4080 we can have
different frequencies for FMAN and PME IP blocks.  We need to keep track
of the FMAN & PME frequencies since they are used for time stamping
capabilities inside each block.

Signed-off-by: Kumar Gala

ppc/p4080: Handle timebase enabling and frequency reporting

2009-09-24T17:05:29+00:00

On CoreNet style platforms the timebase frequency is the bus frequency
defined by 16 (on PQ3 it is divide by 8).  Also on the CoreNet platforms
the core not longer controls the enabling of the timebase.  We now need
to enable the boot core's timebase via CCSR register writes.

Signed-off-by: Kumar Gala

ppc/85xx: Clean up do_reset

2009-09-08T18:47:18+00:00

There is no reason to do a run time check for e500 v1 based cores to
determine if we have the GUTs RSTCR facility.  Only the first generation
of PQ3 parts (MPC8540/41/55/60) do not have it.  So checking to see if
we are e500 v2 would miss future parts (like e500mc).

Just change this to be ifdef'd based on CONFIG_MPC85{40,41,55,60}.

Signed-off-by: Kumar Gala

ppc/85xx/86xx: Bug fix: call to puts in probecpu() moved to checkcpu().

2009-09-08T14:10:08+00:00

While in probecpu() UART is still not initialized.

Signed-off-by: Poonam Aggrwal 
Signed-off-by: Kumar Gala

ppc/85xx,86xx: Handling Unknown SOC version

2009-09-08T14:10:08+00:00

Incase the system is detected with Unknown SVR, let the system boot
with a default value and a proper message.

Now with dynamic detection of SOC properties from SVR, this is necessary
to prevent a crash.

Signed-off-by: Poonam Aggrwal 
Signed-off-by: Kumar Gala

8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xx

2009-08-28T22:12:38+00:00

The number of CPUs are getting detected dynamically by checking the
processor SVR value.  Also removed CONFIG_NUM_CPUS references from all
the platforms with 85xx/86xx processors.

This can help to use the same u-boot image across the platforms.

Also revamped and corrected few Freescale Copyright messages.

Signed-off-by: Poonam Aggrwal 
Signed-off-by: Kumar Gala

8xxx: Refactored common cpu specific code for 85xx/86xx into one file.

2009-08-28T22:12:38+00:00

Removed same code pieces from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c
and moved to cpu/mpc8xxx/cpu.c(new file)

Signed-off-by: Poonam Aggrwal 
Signed-off-by: Kumar Gala

8xxx: Break out DMA code to a common file

2009-07-02T04:01:51+00:00

DMA support is now enabled via the CONFIG_FSL_DMA define instead of the
previous CONFIG_DDR_ECC

Signed-off-by: Peter Tyser 
Signed-off-by: Kumar Gala

fsl/85xx, 86xx: Sync up DMA code

2009-06-12T22:17:58+00:00

The following changes were made to sync up the DMA code between the 85xx
and 86xx architectures which will make it easier to break out common
8xxx DMA code:

85xx:
- Don't set STRANSINT and SPCIORDER fields in SATR register.  These bits
  only have an affect when the SBPATMU bit is set.
- Write 0xffffffff instead of 0xfffffff to clear errors in the DMA
  status register.  We may as well clear all 32 bits of the register...

86xx:
- Add CONFIG_SYS_MPC86xx_DMA_ADDR define to address DMA registers
- Add clearing of errors in the DMA status register when initializing
  the controller
- Clear the channel start bit in the DMA mode register after a transfer

Signed-off-by: Peter Tyser 
Signed-off-by: Kumar Gala