u-boot.git/cpu/mpc85xx/cpu.c, branch v2009.08

8xxx: Break out DMA code to a common file

2009-07-02T04:01:51+00:00

DMA support is now enabled via the CONFIG_FSL_DMA define instead of the
previous CONFIG_DDR_ECC

Signed-off-by: Peter Tyser 
Signed-off-by: Kumar Gala

fsl/85xx, 86xx: Sync up DMA code

2009-06-12T22:17:58+00:00

The following changes were made to sync up the DMA code between the 85xx
and 86xx architectures which will make it easier to break out common
8xxx DMA code:

85xx:
- Don't set STRANSINT and SPCIORDER fields in SATR register.  These bits
  only have an affect when the SBPATMU bit is set.
- Write 0xffffffff instead of 0xfffffff to clear errors in the DMA
  status register.  We may as well clear all 32 bits of the register...

86xx:
- Add CONFIG_SYS_MPC86xx_DMA_ADDR define to address DMA registers
- Add clearing of errors in the DMA status register when initializing
  the controller
- Clear the channel start bit in the DMA mode register after a transfer

Signed-off-by: Peter Tyser 
Signed-off-by: Kumar Gala

fsl: Create common fsl_dma.h for 85xx and 86xx cpus

2009-06-12T22:17:45+00:00

Break out DMA structures for the Freescale MPC85xx and MPC86xx cpus to
reduce a large amount of code duplication

Signed-off-by: Peter Tyser 
Signed-off-by: Kumar Gala

qe: Pass in uec_info struct through uec_initialize

2009-06-12T22:17:02+00:00

The uec driver contains code to hard code configuration information for the uec
ethernet controllers. This patch creates an array of uec_info structures, which
are then parsed by the corresponding driver instance to determine configuration.
It also creates function uec_standard_init() to initialize all UEC interfaces
for 83xx and 85xx.

Signed-off-by: Haiying Wang 
Signed-off-by: Kumar Gala

85xx: Add QE clk support

2009-06-12T22:16:59+00:00

Signed-off-by: Haiying Wang 
Acked-by: Timur Tabi 
Signed-off-by: Kumar Gala

85xx: Added MPC8535/E identifiers

2009-06-12T22:16:26+00:00

Signed-off-by: Kumar Gala

MPC85xx: Add MPC8569 CPU support

2009-03-30T18:33:51+00:00

There is a workaround for MPC8569 CPU Errata, which needs to set Bit 13 of
LBCR in 4K bootpage. We setup a temp TLB for eLBC controller in bootpage,
then invalidate it after LBCR bit 13 is set.

Signed-off-by: Haiying Wang 
Signed-off-by: Kumar Gala

Coding style cleanup, update CHANGELOG

2009-02-18T23:41:08+00:00

Signed-off-by: Wolfgang Denk

85xx: Add eSDHC support for 8536 DS

2009-02-17T00:07:43+00:00

Signed-off-by: Andy Fleming

mpc85xx: Add support for the P2020

2009-02-17T00:05:55+00:00

Added various p2020 processor specific details:
* SVR for p2020, p2020E
* immap updates for LAWs and DDR on p2020
* LAW defines related to p2020

Signed-off-by: Srikanth Srinivasan 
Signed-off-by: Travis Wheatley 
Signed-off-by: Kumar Gala