u-boot.git/cpu/mpc85xx/cpu_init.c, branch master

ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU

2010-04-13T07:13:16+00:00

Signed-off-by: Peter Tyser

ppc/85xx: Add tracking of TLB CAM usage

2010-01-05T19:49:08+00:00

We need to track which TLB CAM entries are used to allow us to
"dynamically" allocate entries later in the code.  For example the SPD
DDR code today hard codes which TLB entries it uses.  We can now make
that pick entries that are free.

Signed-off-by: Kumar Gala

85xx: Add support for e500mc cache stashing

2010-01-05T19:49:02+00:00

The e500mc core supports the ability to stash into the L1 or L2 cache,
however we need to uniquely identify the caches with an id.

We use the following equation to set the various stash-ids:

32 + coreID*2 + 0(L1) or 1(L2)

The 0 (for L1) or 1 (for L2) matches the CT field used be various cache
control instructions.

Signed-off-by: Kumar Gala

ppc/85xx: Make L2 support more robust

2009-10-27T02:24:51+00:00

According the user manual, we need loop-check the L2 enable bit set.

Signed-off-by: Dave Liu 
Signed-off-by: Kumar Gala

ppc/p4080: Handle timebase enabling and frequency reporting

2009-09-24T17:05:29+00:00

On CoreNet style platforms the timebase frequency is the bus frequency
defined by 16 (on PQ3 it is divide by 8).  Also on the CoreNet platforms
the core not longer controls the enabling of the timebase.  We now need
to enable the boot core's timebase via CCSR register writes.

Signed-off-by: Kumar Gala

ppc/85xx: Fix enabling of L2 cache

2009-09-24T17:05:27+00:00

We need to flash invalidate the locks in addition to the cache
before we enable.

Signed-off-by: Kumar Gala

ppc/85xx: Disable all async interrupt sources when we boot

2009-09-16T02:30:09+00:00

We should make sure to clear MSR[ME, CE, DE] when we boot an OS image
since we have changed the exception vectors and the OSes vectors might
not be setup we should avoid async interrupts at all costs.

Signed-off-by: Kumar Gala

ppc/85xx: Split out cpu_init_early into its own file for NAND_SPL

2009-09-16T02:30:09+00:00

By pulling out cpu_init_early we can build just it and not all of
cpu_init for NAND_SPL.

Signed-off-by: Kumar Gala

ppc/85xx: Change cpu_init_early_f so we can use with NAND SPL

2009-09-16T02:30:09+00:00

Use write_tlb and don't use memset so we can use the same code for
cpu_init_early_f between NAND SPL and not.

Signed-off-by: Kumar Gala

ppc/85xx: add boot from NAND/eSDHC/eSPI support

2009-09-16T02:30:09+00:00

The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch
implements these three bootup methods in a unified way - all of these
use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM
which lets us use the SPD to initialize the SDRAM.

For all three bootup methods, the bootup process can be divided into two
stages: the first stage will initialize the corresponding controller,
configure the L2SRAM, then copy the second stage image to L2SRAM and
jump to it. The second stage image is just like the general U-Boot image
to configure all the hardware and boot up to U-Boot command line.

When boot from NAND, the eLBC controller will first load the first stage
image to internal 4K RAM buffer because it's also stored on the NAND
flash. The first stage image, also call 4K NAND loader, will initialize
the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K
NAND loader's code comes from the corresponding nand_spl directory, along
with the code twisted by CONFIG_NAND_SPL.

When boot from eSDHC/eSPI, there's no such a first stage image because
the CPU ROM code does the same work. It will initialize the L2SRAM
according to the config addr/word pairs on the fixed address and
initialize the eSDHC/eSPI controller, then load the second stage image
to L2SRAM and jump to it.

The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the
second stage image for all different bootup methods. It's set in the
board config file when one of the bootup methods above is selected.

Signed-off-by: Mingkai Hu 
Signed-off-by: Kumar Gala