u-boot.git/cpu/mpc85xx/cpu_init.c, branch v1.3.3

85xx: Use SVR_SOC_VER instead of SVR_VER

2008-04-11T22:32:51+00:00

The recent change introduced by 'Update SVR numbers to expand support'
now requires that we use SVR_SOC_VER instead of SVR_VER if we want
to compare against a particular processor id.

Signed-off-by: Kumar Gala

85xx: Added support for multicore boot mechanism

2008-03-26T16:43:03+00:00

Added the cpu command that provides a generic mechanism to get status,
reset, and release secondary cores in multicore processors.

Added support for using the ePAPR defined spin-table mechanism on 85xx.

Signed-off-by: Kumar Gala

85xx: Add the concept of CFG_CCSRBAR_PHYS

2008-03-26T16:43:03+00:00

When we go to 36-bit physical addresses we need to keep the concept of
the physical CCSRBAR address seperate from the virtual one.

For the majority of boards CFG_CCSBAR_PHYS == CFG_CCSRBAR

Signed-off-by: Kumar Gala

85xx: Get ride of old TLB setup code

2008-01-17T08:19:18+00:00

Now that all boards have been converted, remove old config code and the
config option for the new style.

Signed-off-by: Kumar Gala

85xx: Reworked initial processor init

2008-01-17T08:04:53+00:00

Reworked the initial processor initialzation sequence:
* introduced cpu_early_init_f that is run in address space 1 (AS=1)
* Moved TLB/LAW and CCSR init into cpu_early_init_f()
* Reworked initial asm code to do most of the core init before TLBs

The main reasons for these changes are to allow handling of 36-bit phys
addresses in the future and some of the issues that will exist when we
do that.

There are a few caveats on what can be initialized via the LAW and TLB
static tables:
* TLB entry 14/15 can't be initialized via the TLB table
* any LAW that covers the implicit boot window (4G-8M to 4G) must map to
  the code that is currently executing.

Signed-off-by: Kumar Gala

85xx: Move LAW init code into C

2008-01-17T05:21:55+00:00

Move the initialization of the LAWs into C code and provide an API
to allow modification of LAWs after init.

Board code is responsible to provide a law_table and num_law_entries.

We should be able to use the same code on 86xx as well.

Signed-off-by: Kumar Gala

Stop using immap_t on 85xx

2007-12-12T04:34:20+00:00

In the future the offsets to various blocks may not be in same location.
Move to using CFG_MPC85xx_*_ADDR as the base of the registers
instead of getting it via &immap.

Signed-off-by: Kumar Gala

Stop using immap_t for cpm offset on 85xx

2007-12-12T04:34:19+00:00

In the future the offsets to various blocks may not be in same location.
Move to using CFG_MPC85xx_CPM_ADDR as the base of the CPM registers
instead of getting it via &immap->im_cpm.

Signed-off-by: Kumar Gala

Enable L2 cache for MPC8568MDS board

2007-08-29T05:11:44+00:00

The L2 cache size is 512KB for 8568, print out the correct informaiton.

Signed-off-by: Haiying Wang

Add support for UEC to 8568

2007-08-14T06:47:44+00:00

Signed-off-by: Haiying Wang 
Signed-off-by: Andy Fleming