u-boot.git/cpu/mpc85xx/mp.c, branch v2009.11

85xx: MP Boot Page Translation update

2009-10-27T14:34:57+00:00

This change has 3 goals:
- Have secondary cores be released into spin loops at their 'true'
  address in SDRAM.  Previously, secondary cores were put into spin
  loops in the 0xfffffxxx address range which required that boot page
  translation was always enabled while cores were in their spin loops.

- Allow the TLB window that the primary core uses to access the
  secondary cores boot page to be placed at any address.  Previously, a
  TLB window at 0xfffff000 was always used to access the seconary cores'
  boot page.  This TLB address requirement overlapped with other
  peripherals on some boards (eg XPedite5370).  By default, the boot
  page TLB will still use the 0xfffffxxx address range, but this can be
  overridden on a board-by-board basis by defining a custom
  CONFIG_BPTR_VIRT_ADDR.  Note that the TLB used to map the boot page
  remains in use while U-Boot executes.  Previously it was only
  temporarily used, then restored to its initial value.

- Allow Boot Page Translation to be disabled on bootup.  Previously,
  Boot Page Translation was always left enabled after secondary cores
  were brought out of reset.  This caused the 0xfffffxxx address range
  to somewhat "magically" be translated to an address in SDRAM.  Some
  boards may not want this oddity in their memory map, so defining
  CONFIG_MPC8xxx_DISABLE_BPTR will turn off Boot Page Translation after
  the secondary cores are initialized.

These changes are only applicable to 85xx boards with CONFIG_MP defined.

Signed-off-by: Peter Tyser 
Signed-off-by: Kumar Gala

ppc/p4080: CoreNet platfrom style secondary core release

2009-09-24T17:05:28+00:00

The CoreNet platform style of bringing secondary cores out of reset is
a bit different that the PQ3 style.  Mostly the registers that we use
to setup boot translation, enable time bases, and boot release the cores
have moved around.

Signed-off-by: Kumar Gala

ppc/85xx: Fix bug in setup_mp code

2009-09-08T14:10:06+00:00

Its possible that we try and copy the boot page code out of flash into a
DDR location that doesn't have a TLB cover it.  For example, if we have
3G of DDR we typically only map the first 2G.  In the cases of 4G+ this
wasn't an issue since the reset page TLB mapping covered the last page
of memory which we wanted to copy to.

We now change the physical address of the reset page TLB to map to the
true physical location of the boot page code, copy and than set the
TLB back to its 1:1 mapping of the reset page.

Signed-off-by: Kumar Gala

8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xx

2009-08-28T22:12:38+00:00

The number of CPUs are getting detected dynamically by checking the
processor SVR value.  Also removed CONFIG_NUM_CPUS references from all
the platforms with 85xx/86xx processors.

This can help to use the same u-boot image across the platforms.

Also revamped and corrected few Freescale Copyright messages.

Signed-off-by: Poonam Aggrwal 
Signed-off-by: Kumar Gala

85xx: Introduce determine_mp_bootpg() helper.

2009-04-01T20:29:49+00:00

Match determine_mp_bootpg() that was added for 86xx.  We need this to
address a bug introduced in v2009.03 with 86xx MP booting.  We have to
make sure to reserve the region of memory used for the MP bootpg() so
other u-boot code doesn't use it.

Also added a comment about how cpu_reset() is dealing w/an errata on
early 85xx MP HW.

Signed-off-by: Kumar Gala

rename CFG_ macros to CONFIG_SYS

2008-10-18T19:54:03+00:00

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD

85xx: Rename CONFIG_NR_CPUS to CONFIG_NUM_CPUS

2008-08-11T22:09:29+00:00

Use CONFIG_NUM_CPUS to match existing define used by 86xx.

Signed-off-by: Kumar Gala 
Acked-by: Jon Loeliger

Fix some more printf() format problems.

2008-07-14T21:01:01+00:00

Signed-off-by: Kumar Gala

85xx: Additional fixes and cleanup of MP code

2008-04-29T14:42:19+00:00

* adjust __spin_table alignment to match ePAPR v0.94 spec
* loop over all cpus when determing who is up.  This fixes an issue if
  the "boot cpu" isn't core0.  The "boot cpu" will already be in the
  cpu_up_mask so there is no harm
* Added some protection in the code to ensure proper behavior.  These
  changes are explicitly needed but don't hurt:
  - Added eieio to ensure the "hot word" of the table is written after
    all other table updates have occurred.
  - Added isync to ensure we don't prefetch loading of table entries
    until we a released

These issues we raised by Dave Liu.

Signed-off-by: Kumar Gala

85xx: Fix detection of MP cpu spin up

2008-04-11T22:32:56+00:00

We were looking at the wrong memory offset to determine of a secondary
cpu had been spun up or not.  Also added a warning message if the
all the secondary cpus we expect don't spin up.

Signed-off-by: Kumar Gala