u-boot.git/cpu/mpc85xx/release.S, branch master

ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU

2010-04-13T07:13:16+00:00

Signed-off-by: Peter Tyser

85xx: Set HID1[mbdd] on e500v2 rev5.0 or greater

2010-04-07T05:21:27+00:00

The HID1[MBDD] bit is new on rev5.0 or greater cores and will optimize
the performance of mbar/eieio instructions.

Signed-off-by: Sandeep Gopalpet

85xx: Add defines for BUCSR bits to make code more readable

2010-04-07T05:08:17+00:00

Signed-off-by: Kumar Gala

85xx: Fix enabling of L1 cache parity on secondary cores

2010-03-30T15:48:30+00:00

Use the same code between primary and secondary cores to init the
L1 cache.  We were not enabling cache parity on the secondary cores.

Also, reworked the L1 cache init code to match the e500mc L2 init code
that first invalidates the cache and locks.  Than enables the cache and
makes sure its enabled before continuing.

Signed-off-by: Kumar Gala

ppc/85xx: Map boot page guarded for MP boot

2010-01-05T19:49:09+00:00

We already map the page cache-inhibited.  There is no reason we
shouldn't also be marking it guarded to prevent speculative accesses.

Signed-off-by: Kumar Gala

85xx: Add support for e500mc cache stashing

2010-01-05T19:49:02+00:00

The e500mc core supports the ability to stash into the L1 or L2 cache,
however we need to uniquely identify the caches with an id.

We use the following equation to set the various stash-ids:

32 + coreID*2 + 0(L1) or 1(L2)

The 0 (for L1) or 1 (for L2) matches the CT field used be various cache
control instructions.

Signed-off-by: Kumar Gala

ppc/85xx: Fix misc L2 cache enabling bug

2009-10-31T15:59:52+00:00

We need loop-check the flash clear lock and enable bit for L2 cache.

Signed-off-by: Dave Liu 
Signed-off-by: Kumar Gala

85xx: MP Boot Page Translation update

2009-10-27T14:34:57+00:00

This change has 3 goals:
- Have secondary cores be released into spin loops at their 'true'
  address in SDRAM.  Previously, secondary cores were put into spin
  loops in the 0xfffffxxx address range which required that boot page
  translation was always enabled while cores were in their spin loops.

- Allow the TLB window that the primary core uses to access the
  secondary cores boot page to be placed at any address.  Previously, a
  TLB window at 0xfffff000 was always used to access the seconary cores'
  boot page.  This TLB address requirement overlapped with other
  peripherals on some boards (eg XPedite5370).  By default, the boot
  page TLB will still use the 0xfffffxxx address range, but this can be
  overridden on a board-by-board basis by defining a custom
  CONFIG_BPTR_VIRT_ADDR.  Note that the TLB used to map the boot page
  remains in use while U-Boot executes.  Previously it was only
  temporarily used, then restored to its initial value.

- Allow Boot Page Translation to be disabled on bootup.  Previously,
  Boot Page Translation was always left enabled after secondary cores
  were brought out of reset.  This caused the 0xfffffxxx address range
  to somewhat "magically" be translated to an address in SDRAM.  Some
  boards may not want this oddity in their memory map, so defining
  CONFIG_MPC8xxx_DISABLE_BPTR will turn off Boot Page Translation after
  the secondary cores are initialized.

These changes are only applicable to 85xx boards with CONFIG_MP defined.

Signed-off-by: Peter Tyser 
Signed-off-by: Kumar Gala

ppc/85xx: Fix enabling of L2 cache

2009-09-24T17:05:27+00:00

We need to flash invalidate the locks in addition to the cache
before we enable.

Signed-off-by: Kumar Gala

85xx: Add support for setting IVORs to fixed offset defaults

2009-09-08T14:10:05+00:00

In future Book-E implementations IVORs will most likely go away and be
replaced with fixed offsets.  The IVPR will continue to exist to allow
for relocation of the interrupt vectors.

This code adds support to setup the IVORs as their fixed offset values
per the ISA 2.06 spec when we transition from u-boot to another OS
either via 'bootm' or a cpu release.

Signed-off-by: Kumar Gala