u-boot.git/cpu/mpc85xx/speed.c, branch master

ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU

2010-04-13T07:13:16+00:00

Signed-off-by: Peter Tyser

Fix the local bus divider mapping

2010-01-26T04:14:39+00:00

The real clock divider is 4 times of the bits LCRR[CLKDIV],
according the latest RevF RM.

Signed-off-by: Dave Liu 
Signed-off-by: Kumar Gala

Revert "ppc/p4080: Fix reporting of PME & FM clock frequencies"

2010-01-26T04:13:25+00:00

This reverts commit bc20f9a9527afe8ae406a74f74765d4323f04922.

The original code was correct.  I clearly need glasses or a brown
paper bag.

Signed-off-by: Kumar Gala

ppc/p4080: Fix mask width of RCW fields MEM_PLL_RAT, SYS_PLL_RAT

2010-01-26T04:13:25+00:00

The masks for MEM_PLL_RAT and SYS_PLL_RAT should have been 5-bits
instead of 4.

Signed-off-by: James Yang 
Signed-off-by: Kumar Gala

ppc/p4080: Fix reporting of PME & FM clock frequencies

2010-01-05T19:49:10+00:00

We incorrectly had the sense of PME_CLK_SEL, FM1_CLK_SEL, FM2_CLK_SEL
backwards so we report the wrong frequency.

Signed-off-by: Kumar Gala

mpc85xx: Add eSDHC support for MPC8569E-MDS boards

2009-10-27T14:36:48+00:00

eSDHC is mutually exlusive with UART0 (in 4-bits mode) and I2C2
(in 1-bit mode). When eSDHC is used, we should switch u-boot console to
UART1, and make the proper device-tree fixups.

Because of an erratum in prototype boards it is impossible to use eSDHC
without disabling UART0 (which makes it quite easy to 'brick' the board
by simply issung 'setenv hwconfig esdhc', and not able to interact with
U-Boot anylonger).

So, but default we assume that the board is a prototype, which is a most
safe assumption. There is no way to determine board revision from a
register, so we use hwconfig.

Signed-off-by: Anton Vorontsov 
Signed-off-by: Kumar Gala

ppc/p4080: Determine various chip frequencies on CoreNet platforms

2009-09-24T17:05:29+00:00

The means to determine the core, bus, and DDR frequencies are completely
new on CoreNet style platforms.  Additionally on p4080 we can have
different frequencies for FMAN and PME IP blocks.  We need to keep track
of the FMAN & PME frequencies since they are used for time stamping
capabilities inside each block.

Signed-off-by: Kumar Gala

ppc/85xx: Use CONFIG_FSL_ESDHC to enable sdhc clk

2009-09-08T14:10:02+00:00

Enable eSDHC Clock based on generic CONFIG_FSL_ESDHC define instead of a
platform define.  This will enable all the 85xx platforms to use sdhc_clk
based on CONFIG_FSL_ESDHC.

Signed-off-by: Gao Guanhua 
Signed-off-by: Dipen Dudhat 
Signed-off-by: Kumar Gala

8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xx

2009-08-28T22:12:38+00:00

The number of CPUs are getting detected dynamically by checking the
processor SVR value.  Also removed CONFIG_NUM_CPUS references from all
the platforms with 85xx/86xx processors.

This can help to use the same u-boot image across the platforms.

Also revamped and corrected few Freescale Copyright messages.

Signed-off-by: Poonam Aggrwal 
Signed-off-by: Kumar Gala

85xx: Add QE clk support

2009-06-12T22:16:59+00:00

Signed-off-by: Haiying Wang 
Acked-by: Timur Tabi 
Signed-off-by: Kumar Gala