u-boot.git/cpu/mpc85xx/start.S, branch U-Boot-1_2_0

Fix bug in [id]cache_status commands for MPC85xx processors;

2006-03-12T23:46:05Z

should look at LSB of L1CSRn registers to determine if L1 cache is enabled, not the MSB. Patch by Murray Jensen, 19 Jul 2005

Added support for KwikByte KB920x boards (based on AT91RM9200)

2005-10-04T22:19:34Z

Patch by Matt ?? , 27 Apr 2005

E500 update: repoint IVPR to RAM when code is relocated

2005-10-04T22:00:54Z

Patch by Kylo Ginsberg, 13 Apr 2005

Merge with /home/wd/git/u-boot/master

2005-08-05T09:22:28Z

Fix typos in cpu/85xx/start.S which caused DataTLB exception to be

2005-08-03T23:24:19Z

routed to the Watchdog handler Patch by Eugene Surovegin, 18 Jun 2005

* Patch by Ron Alder, 11 July 2005

2005-07-29T15:20:29Z

Add Xianghua Xiao and Lunsheng Wang's support for the GDA MPC8540 EVAL board.

* Patch by Jon Loeliger, 2005-05-05

2005-07-25T19:05:07Z

Implemented support for MPC8548CDS board. Added DDR II support based on SPD values for MPC85xx boards. This roll-up patch also includes bugfies for the previously published patches: DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O

Fix timer handling on MPC85xx systems

2005-05-13T22:49:36Z

Patch by Jon Loeliger, 16 Jul 2004:

2004-08-01T23:02:45Z

- support larger DDR memories up to 2G on the PC8540/8560ADS and STXGP3 boards - Made MPC8540/8560ADS be 33Mhz PCI by default. - Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16 and CONFIG_L2_INIT_RAM options. - Refactor Local Bus initialization out of SDRAM setup. - Re-implement new version of LBC11/DDR11 errata workarounds. - Moved board specific PCI init parts out of CPU directory. - Added TLB entry for PCI-1 IO Memory - Updated README.mpc85xxads

Patch by Jon Loeliger, 17 June 2004:

2004-07-09T23:27:13Z

Completion of the 8540ADS/8560ADS updates: Fix some PCI and Rapid I/O memory maps, Initialize both TSEC 1 and 2, Initialize SDRAM Update MAINTAINER for 85xx boards and README.mpc85xxads