u-boot.git/cpu/mpc85xx, branch v1.3.0 Unnamed repository; edit this file 'description' to name the repository. Cleanup coding style; update CHANGELOG 2007-11-03T22:09:27+00:00 Wolfgang Denk wd@denx.de 2007-11-03T22:09:27+00:00 992742a5b09d9040adbd156fb90756af66ade310 Signed-off-by: Wolfgang Denk <wd@denx.de> 
Signed-off-by: Wolfgang Denk <wd@denx.de>
Setting MSR[DE] in do_reset 2007-10-19T18:13:44+00:00 urwithsughosh@gmail.com urwithsughosh@gmail.com 2007-09-24T17:32:13+00:00 df90968b48fb34fa9072fab150db2ac89678f537 Hello, This patch ensures the soft reset of the board for the 85xx boards by setting the MSR[DE] in the do_reset function. Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com> 
Hello,
   This patch ensures the soft reset of the board for the 85xx boards
   by setting the MSR[DE] in the do_reset function.

Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
MSR overwrite fix 2007-10-19T18:13:27+00:00 urwithsughosh@gmail.com urwithsughosh@gmail.com 2007-09-24T17:36:01+00:00 1e701e701304b3c3a3768ca83dd2ab7b9e88c77d Hello, This patch fixes the MSR overwrite in the start.S when moving out of the last 4K page. Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com> 
Hello,
  This patch fixes the MSR overwrite in the start.S when moving out of
  the last 4K page.

Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
Remove magic numbers from cache related operations for mpc85xx 2007-10-19T16:25:01+00:00 Kumar Gala galak@kernel.crashing.org 2007-10-02T16:12:27+00:00 e1ce3cb617bb06f91f82f98915391175addf3e82 The mpc85xx start code uses some magic numbers that we actually have #defines for in <config.h> so use those instead. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
The mpc85xx start code uses some magic numbers that we actually
have #defines for in <config.h> so use those instead.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
85xx io out functions need sync after write. 2007-09-26T21:50:02+00:00 Ed Swarthout Ed.Swarthout@freescale.com 2007-09-26T21:35:54+00:00 1487adbdcf9594bb2eb686325a6f9540dad1b70a This fixes the mc146818 rtc_read/write functions for 85xx. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> 
This fixes the mc146818 rtc_read/write functions for 85xx.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Enable L2 cache for MPC8568MDS board 2007-08-29T05:11:44+00:00 Haiying Wang Haiying.Wang@freescale.com 2007-08-23T19:20:54+00:00 7a1ac419fa0d2d23ddd08bd61d16896a9f33c933 The L2 cache size is 512KB for 8568, print out the correct informaiton. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> 
The L2 cache size is 512KB for 8568, print out the correct informaiton.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
85xxCDS: Add make targets for legacy systems. 2007-08-14T06:51:39+00:00 Randy Vinson rvinson@linuxbox.(none) 2007-02-28T02:42:22+00:00 7f3f2bd2dc08e0b05e185662ca2e2d283757104a The PCI ID select values on the Arcadia main board differ depending on the version of the hardware. The standard configuration supports Rev 3.1. The legacy target supports Rev 2.x. Signed-off-by Randy Vinson <rvinson@mvista.com> 
The PCI ID select values on the Arcadia main board differ depending
on the version of the hardware. The standard configuration supports
Rev 3.1. The legacy target supports Rev 2.x.

Signed-off-by Randy Vinson <rvinson@mvista.com>
Add support for UEC to 8568 2007-08-14T06:47:44+00:00 Andy Fleming afleming@freescale.com 2007-08-14T05:14:25+00:00 da9d4610d76e52c4d20a8f3d8433439a7fcf5b71 Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> 
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Empirically set cpo and clk_adjust for mpc85xx DDR2 support 2007-08-14T06:45:51+00:00 Haiying Wang Haiying.Wang@freescale.com 2007-06-19T18:18:32+00:00 d111d6382c99fdea08c2312eeeae8786945e189a This patch is against u-boot-mpc85xx.git of www.denx.com Setting cpo to 0x9 for frequencies higher than 333MHz is verified on both MPC8548CDS board and MPC8568MDS board, especially for supporting 533MHz DDR2. Setting clk_adjust to 0x6(3/4 late cycle) for MPC8568MDS board is for DDR2 on all current board versions especially ver 1.92 or later to bring up. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> 
This patch is against u-boot-mpc85xx.git of www.denx.com

Setting cpo to 0x9 for frequencies higher than 333MHz is verified on
both MPC8548CDS board and MPC8568MDS board, especially for supporting
533MHz DDR2.

Setting clk_adjust to 0x6(3/4 late cycle) for MPC8568MDS board is for
DDR2 on all current board versions especially ver 1.92 or later to bring
up.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Use an absolute address when jumping out of 4k boot page 2007-08-14T06:45:09+00:00 Kumar Gala galak@kernel.crashing.org 2007-08-07T23:07:27+00:00 3db0bef59eab1155801618cef5c481e97553b597 On e500 when we leave the 4k boot page we should use an absolute address since we don't know where the board code may want us to be really running at. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
On e500 when we leave the 4k boot page we should use an absolute address since
we don't know where the board code may want us to be really running at.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>