u-boot.git/cpu/mpc85xx, branch v1.3.2

85xx: Don't icbi when unlocking the cache

2008-02-27T22:30:47+00:00

There is no reason to icbi when invalidating the temporary stack in
the d-cache.  Its impossible on e500 to have the i-cache contain
any addresses in the temp stack and it can be problematic in generating
transactions on the bus to non-valid addresses.

Signed-off-by: Kumar Gala

Fix source for ECM error IVPR

2008-02-27T22:28:57+00:00

The source vector for the ECM was being set to 2,
but that's what the source vector for DDR was being
set to.  Change it to 1.

Signed-off-by: Andy Fleming

Invalidate INIT_RAM TLB mappings

2008-02-27T22:28:48+00:00

Commit 0db37dc...  (and some others) changed the INIT_RAM TLB
mappings to be unguarded.  This collided with an existing "bug"
where the mappings for the INIT_RAM were being kept around.
This meant that speculative loads to those addresses were
succeeding in the TLB, and going out to the bus, where they
were causing an exception (there's nothing at that address). The
Flash code was coincidentally causing such a speculative load.
Rather than go back to mapping the INIT RAM as guarded, we fix
it so that the entries for the INIT_RAM are invalidated.  Thus
the speculative loads will fail in the TLB, and have no effect.

Signed-off-by: Andy Fleming

85xx, 86xx: Determine I2C clock frequencies and store in global_data

2008-02-14T22:32:40+00:00

Update global_data to define i2c1_clk and i2c2_clk to 85xx and 86xx.

Update the get_clocks() function in 85xx and 86xx to determine the I2C
clock frequency and store it in gd->i2c1_clk and gd->i2c2_clk.

Signed-off-by: Timur Tabi

PPC: Use r2 instead of r29 as global data pointer

2008-02-14T21:43:22+00:00

R29 was an unlucky choice as with recent toolchains (gcc-4.2.x) gcc
will refuse to use load/store multiple insns; instead, it issues a
list of simple load/store instructions upon function entry and exit,
resulting in bigger code size, which in turn makes the build for a
few boards fail.

Use r2 instead.

Signed-off-by: Wolfgang Denk

ppc: Refactor cache routines, so there is only one common set.

2008-02-14T21:00:41+00:00

Signed-off-by: Rafal Jaworowski

QE: Move FDT support into a common file

2008-02-11T23:36:21+00:00

Move the flat device tree setup for QE related devices into
a common file shared between 83xx & 85xx platforms that have QE's.

Signed-off-by: Kumar Gala

Coding Style Cleanup; update CHANGELOG

2008-01-23T13:31:17+00:00

Signed-off-by: Wolfgang Denk

85xx: Get ride of old TLB setup code

2008-01-17T08:19:18+00:00

Now that all boards have been converted, remove old config code and the
config option for the new style.

Signed-off-by: Kumar Gala

85xx: Reworked initial processor init

2008-01-17T08:04:53+00:00

Reworked the initial processor initialzation sequence:
* introduced cpu_early_init_f that is run in address space 1 (AS=1)
* Moved TLB/LAW and CCSR init into cpu_early_init_f()
* Reworked initial asm code to do most of the core init before TLBs

The main reasons for these changes are to allow handling of 36-bit phys
addresses in the future and some of the issues that will exist when we
do that.

There are a few caveats on what can be initialized via the LAW and TLB
static tables:
* TLB entry 14/15 can't be initialized via the TLB table
* any LAW that covers the implicit boot window (4G-8M to 4G) must map to
  the code that is currently executing.

Signed-off-by: Kumar Gala