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<title>u-boot.git/cpu/mpc85xx, branch v1.3.3</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>85xx: Add -mno-spe to e500/85xx builds</title>
<updated>2008-04-29T18:08:43+00:00</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2008-04-29T17:54:59+00:00</published>
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<id>70a0f81412b0b18a6fd0bea960451bc6c2cca49a</id>
<content type='text'>
Newer gcc's might be configured to enable autovectorization by default.
If we happen to build with one of those compilers we will get SPE
instructions in random code.

-mno-spe disables the compiler for automatically generating SPE
instructions without our knowledge.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
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<pre>
Newer gcc's might be configured to enable autovectorization by default.
If we happen to build with one of those compilers we will get SPE
instructions in random code.

-mno-spe disables the compiler for automatically generating SPE
instructions without our knowledge.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
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</content>
</entry>
<entry>
<title>85xx/86xx: Rename ext_refrec to timing_cfg_3 to match docs</title>
<updated>2008-04-29T16:44:29+00:00</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2008-04-29T15:27:08+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=45239cf4152109caa925145ccd433529902df887'/>
<id>45239cf4152109caa925145ccd433529902df887</id>
<content type='text'>
All the 85xx and 86xx UM describe the register as timing_cfg_3
not as ext_refrec.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
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<pre>
All the 85xx and 86xx UM describe the register as timing_cfg_3
not as ext_refrec.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
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</content>
</entry>
<entry>
<title>85xx: Additional fixes and cleanup of MP code</title>
<updated>2008-04-29T14:42:19+00:00</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2008-04-28T07:24:04+00:00</published>
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<id>cf6cc014270549684873a5972d2595052c468cb6</id>
<content type='text'>
* adjust __spin_table alignment to match ePAPR v0.94 spec
* loop over all cpus when determing who is up.  This fixes an issue if
  the "boot cpu" isn't core0.  The "boot cpu" will already be in the
  cpu_up_mask so there is no harm
* Added some protection in the code to ensure proper behavior.  These
  changes are explicitly needed but don't hurt:
  - Added eieio to ensure the "hot word" of the table is written after
    all other table updates have occurred.
  - Added isync to ensure we don't prefetch loading of table entries
    until we a released

These issues we raised by Dave Liu.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
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<pre>
* adjust __spin_table alignment to match ePAPR v0.94 spec
* loop over all cpus when determing who is up.  This fixes an issue if
  the "boot cpu" isn't core0.  The "boot cpu" will already be in the
  cpu_up_mask so there is no harm
* Added some protection in the code to ensure proper behavior.  These
  changes are explicitly needed but don't hurt:
  - Added eieio to ensure the "hot word" of the table is written after
    all other table updates have occurred.
  - Added isync to ensure we don't prefetch loading of table entries
    until we a released

These issues we raised by Dave Liu.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
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</content>
</entry>
<entry>
<title>85xx: Round up frequency calculations to get reasonable output</title>
<updated>2008-04-24T13:42:35+00:00</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2008-04-21T14:28:36+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=022f12163595b9a55380c6d77c3119b93d6a9a4b'/>
<id>022f12163595b9a55380c6d77c3119b93d6a9a4b</id>
<content type='text'>
eg. because of rounding error we can get 799Mhz instead of 800Mhz.

Introduced DIV_ROUND_UP and roundup taken from linux kernel.

Signed-off-by: Dejan Minic &lt;minic@freescale.com&gt;
Signed-off-by: Srikanth Srinivasan &lt;srikanth.srinivasan@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
Acked-by: Andy Fleming &lt;afleming@freescale.com&gt;
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<pre>
eg. because of rounding error we can get 799Mhz instead of 800Mhz.

Introduced DIV_ROUND_UP and roundup taken from linux kernel.

Signed-off-by: Dejan Minic &lt;minic@freescale.com&gt;
Signed-off-by: Srikanth Srinivasan &lt;srikanth.srinivasan@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
Acked-by: Andy Fleming &lt;afleming@freescale.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>85xx: Fix size of cpu-release-addr property</title>
<updated>2008-04-18T22:44:50+00:00</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2008-04-18T16:29:01+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0878af169b181868a105b5c33f3a6423e2c9fd60'/>
<id>0878af169b181868a105b5c33f3a6423e2c9fd60</id>
<content type='text'>
The cpu-release-addr is defined as always being a 64-bit quanity regardless
if we are running on a 32-bit or 64-bit machine.
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<pre>
The cpu-release-addr is defined as always being a 64-bit quanity regardless
if we are running on a 32-bit or 64-bit machine.
</pre>
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</content>
</entry>
<entry>
<title>Fix calculation of I2C clock for some 85xx chips</title>
<updated>2008-04-18T22:43:09+00:00</updated>
<author>
<name>Timur Tabi</name>
<email>timur@freescale.com</email>
</author>
<published>2008-04-04T16:15:58+00:00</published>
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<id>88353a985109562a639b2f8a0c90d77011bfe374</id>
<content type='text'>
Some 85xx chips use CCB as the base clock for the I2C.  Some use CCB/2, and
some use CCB/3.  There is no pattern that can be used to determine which
chips use which frequency, so the only way to determine is to look up the
actual SOC designation and use the right value for that SOC.

Update immap_85xx.h to include the GUTS PORDEVSR2 register.

Signed-off-by: Timur Tabi &lt;timur@freescale.com&gt;
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<pre>
Some 85xx chips use CCB as the base clock for the I2C.  Some use CCB/2, and
some use CCB/3.  There is no pattern that can be used to determine which
chips use which frequency, so the only way to determine is to look up the
actual SOC designation and use the right value for that SOC.

Update immap_85xx.h to include the GUTS PORDEVSR2 register.

Signed-off-by: Timur Tabi &lt;timur@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>85xx: Fix detection of MP cpu spin up</title>
<updated>2008-04-11T22:32:56+00:00</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2008-04-09T09:20:57+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=97b3ecb575a92fa34c1765229dbc06f2b662f139'/>
<id>97b3ecb575a92fa34c1765229dbc06f2b662f139</id>
<content type='text'>
We were looking at the wrong memory offset to determine of a secondary
cpu had been spun up or not.  Also added a warning message if the
all the secondary cpus we expect don't spin up.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
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<pre>
We were looking at the wrong memory offset to determine of a secondary
cpu had been spun up or not.  Also added a warning message if the
all the secondary cpus we expect don't spin up.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>85xx: Use SVR_SOC_VER instead of SVR_VER</title>
<updated>2008-04-11T22:32:51+00:00</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2008-04-08T15:45:50+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f3e04bdc3f360c66801a9048956e61e41a16edba'/>
<id>f3e04bdc3f360c66801a9048956e61e41a16edba</id>
<content type='text'>
The recent change introduced by 'Update SVR numbers to expand support'
now requires that we use SVR_SOC_VER instead of SVR_VER if we want
to compare against a particular processor id.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
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<pre>
The recent change introduced by 'Update SVR numbers to expand support'
now requires that we use SVR_SOC_VER instead of SVR_VER if we want
to compare against a particular processor id.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>85xx: Add cpu_mp_lmb_reserve helper to reserve boot page</title>
<updated>2008-03-26T16:43:04+00:00</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2008-03-26T13:53:53+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=dd6c910aadf27c822f17b87eae1a9bd0b2e3aa15'/>
<id>dd6c910aadf27c822f17b87eae1a9bd0b2e3aa15</id>
<content type='text'>
Provide a board_lmb_reserve helper function to ensure we reserve
the page of memory we are using for the boot page translation code.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
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<pre>
Provide a board_lmb_reserve helper function to ensure we reserve
the page of memory we are using for the boot page translation code.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>85xx: Update multicore boot mechanism to ePAPR v0.81 spec</title>
<updated>2008-03-26T16:43:04+00:00</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2008-03-26T13:34:25+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=79679d80021ab095e639e250ca472fe526da02e2'/>
<id>79679d80021ab095e639e250ca472fe526da02e2</id>
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The following changes are needed to be inline with ePAPR v0.81:

* r4, r5 and now always set to 0 on boot release
* r7 is used to pass the size of the initial map area (IMA)
* EPAPR_MAGIC value changed for book-e processors
* changes in the spin table layout
* spin table supports a 64-bit physical release address

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
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<pre>
The following changes are needed to be inline with ePAPR v0.81:

* r4, r5 and now always set to 0 on boot release
* r7 is used to pass the size of the initial map area (IMA)
* EPAPR_MAGIC value changed for book-e processors
* changes in the spin table layout
* spin table supports a 64-bit physical release address

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
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