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<title>u-boot.git/cpu/mpc85xx, branch v2008.10</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/cpu/mpc85xx?h=v2008.10</id>
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<updated>2008-10-17T08:50:41Z</updated>
<entry>
<title>Revert "85xx: Using proper I2C source clock divider for MPC8544"</title>
<updated>2008-10-17T08:50:41Z</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2008-10-17T02:58:49Z</published>
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<id>urn:sha1:42653b826adb319a1df06e24ef26096b2a5d9d2a</id>
<content type='text'>
This reverts commit dffd2446fb041f38ef034b0fcf41e51e5e489159.

The fix introduced by this patch is not correct.  The problem is
that the documentation is not correct for the MPC8544 with regards
to which bit in PORDEVSR2 is for the SEC_CFG.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
</entry>
<entry>
<title>85xx: Using proper I2C source clock divider for MPC8544</title>
<updated>2008-10-08T19:20:27Z</updated>
<author>
<name>Wolfgang Grandegger</name>
<email>wg@grandegger.com</email>
</author>
<published>2008-09-30T08:55:57Z</published>
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<id>urn:sha1:dffd2446fb041f38ef034b0fcf41e51e5e489159</id>
<content type='text'>
Measurements with our MPC8544 board showed that the I2C bus frequency
is wrong by a factor of 1.5. Obviously, the interpretation of the
MPC85xx_PORDEVSR2_SEC_CFG bit of the cfg_sec_freq register is not
correct. There seems to be an error in the 8544 RM.

Signed-off-by: Wolfgang Grandegger &lt;wg@grandegger.com&gt;
</content>
</entry>
<entry>
<title>Fix the incorrect DDR clk freq reporting on 8536DS</title>
<updated>2008-10-07T20:37:08Z</updated>
<author>
<name>Jason Jin</name>
<email>Jason.jin@freescale.com</email>
</author>
<published>2008-09-27T06:40:57Z</published>
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<id>urn:sha1:c0391111c33c22fabeddf8f4ca801ec7645b4f5c</id>
<content type='text'>
On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111),
The display is still sync mode DDR freq. This patch try to fix
this. The display DDR freq is now the actual freq in both
sync and async mode.

Signed-off-by: Jason Jin &lt;Jason.jin@freescale.com&gt;
</content>
</entry>
<entry>
<title>85xx: Remove setting of *cache-line-size in device trees</title>
<updated>2008-10-07T15:28:59Z</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2008-10-07T15:28:46Z</published>
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<id>urn:sha1:bac6a1d1fa1cd80aa57881fa9c2152b853cd0ed4</id>
<content type='text'>
ePAPR says if the *cache-block-size is the same as *cache-line-size
than we don't need the *cache-line-size property.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
</entry>
<entry>
<title>Fix printf errors under -DDEBUG</title>
<updated>2008-09-09T22:02:41Z</updated>
<author>
<name>Andrew Klossner</name>
<email>andrew@cesa.opbu.xerox.com</email>
</author>
<published>2008-08-21T14:12:26Z</published>
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<id>urn:sha1:5251469943895de4bb9a04d5053352cc22acb7d5</id>
<content type='text'>
Fix printf format-string/arg mismatches under -DDEBUG.

These warnings occur with DEBUG defined for a platform using
cpu/mpc85xx.  Users of other architectures can unearth similar
problems by adding the line "CFLAGS += -DDEBUG=1" in config.mk right
after "CFLAGS += $(call cc-option,-fno-stack-protector)".

Signed-off-by: Andrew Klossner &lt;andrew@cesa.opbu.xerox.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>85xx: Ensure timebase is zero on secondary cores</title>
<updated>2008-09-09T21:52:45Z</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2008-09-08T13:51:29Z</published>
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<id>urn:sha1:e0ff3d350d6b7960deb5a881dfc5acf3a63ef676</id>
<content type='text'>
The e500um says the timebase is volatile out of reset.  To ensure
TB sync works we need to make sure its zero.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
</entry>
<entry>
<title>Removed hardcoded MxMR loop value from upmconfig() for MPC85xx.</title>
<updated>2008-09-09T00:48:55Z</updated>
<author>
<name>Sergei Poselenov</name>
<email>sposelenov@emcraft.com</email>
</author>
<published>2008-08-15T13:42:11Z</published>
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<id>urn:sha1:6cc64f9b5f69239c8b1969572b5a3a4aab7de5b9</id>
<content type='text'>
Signed-off-by: Sergei Poselenov &lt;sposelenov@emcraft.com&gt;
</content>
</entry>
<entry>
<title>Pass in tsec_info struct through tsec_initialize</title>
<updated>2008-09-03T04:18:15Z</updated>
<author>
<name>Andy Fleming</name>
<email>afleming@freescale.com</email>
</author>
<published>2008-08-31T21:33:26Z</published>
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<id>urn:sha1:75b9d4ae0d69f214eab641caf12ce8af83a39a42</id>
<content type='text'>
The tsec driver contains a hard-coded array of configuration information
for the tsec ethernet controllers.  We create a default function that works
for most tsecs, and allow that to be overridden by board code.  It creates
an array of tsec_info structures, which are then parsed by the corresponding
driver instance to determine configuration.  Also, add regs, miiregs, and
devname fields to the tsec_info structure, so that we don't need the kludgy
"index" parameter.

Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
Signed-off-by: Ben Warren &lt;biggerbadderben@gmail.com&gt;
</content>
</entry>
<entry>
<title>mpc85xx: remove redudant code with lib_ppc/interrupts.c</title>
<updated>2008-08-27T16:44:10Z</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2008-08-19T19:46:36Z</published>
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<id>urn:sha1:9cff4448a9cb882defe6c8bde73b77fc0c636799</id>
<content type='text'>
For some reason we duplicated the majority of code in lib_ppc/interrupts.c
not show how that happened, but there is no good reason for it.

Use the interrupt_init_cpu() and timer_interrupt_cpu() since its why
they exist.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
</entry>
<entry>
<title>mpc85xx: Add support for the MPC8536</title>
<updated>2008-08-27T16:43:54Z</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2008-08-12T16:14:19Z</published>
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<id>urn:sha1:ef50d6c06ece74fb17e8d7510e62cad9df8b810d</id>
<content type='text'>
The MPC8536 Adds SDHC and SATA controllers to the PQ3 family.  We
also have SERDES init code for the 8536.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
Signed-off-by: Srikanth Srinivasan &lt;srikanth.srinivasan@freescale.com&gt;
Signed-off-by: Dejan Minic &lt;minic@freescale.com&gt;
Signed-off-by: Jason Jin &lt;Jason.jin@freescale.com&gt;
Signed-off-by: Dave Liu &lt;daveliu@freescale.com&gt;
</content>
</entry>
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